參數(shù)資料
型號： A42MX16-2BG100B
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 83/120頁
文件大?。?/td> 854K
代理商： A42MX16-2BG100B
65
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The alternate pin configuration on Port D:
SDIN/PCINT23 - Port D, Bit 7
SDIN: Serial Data Input. External serial data input of the SSI on PD7 pin. When in the Timer2
modulator the SPI mode of the SSI is selected (T2M[3..0] = 0b1001), this pin is configured as an
input regardless of the setting of DDD7. When the pin is forced to be an input, the pull-up can
still be controlled by the PORTD7 bit.
PCINT23, Pin Change Interrupt Source 23: The PD7 pin can serve as an external interrupt
source.
T2O2/PCINT22 - Port D, Bit 6
T2O2: Timer2 Output 2. The PD6 pin can serve as an external out for the Timer2 modulator out-
put 2. The function of the modulator output pin is depend on the Timer2 Mode bits T2M[3..0] bits
in the T2MRB register. The PD6 pin has to be configured as an output (DDD6 set [one]) if the
timer mode is used the output pin to serve this function. When PD6 is not used as modulator out-
put pin, it is a I/O pin.
PCINT22, Pin Change Interrupt Source 22: The PD6 pin can serve as an external interrupt
source.
T2O1/PCINT21 - Port D, Bit 5
T2O1: Timer2 Output 1. The PD5 pin can serve as an external out for the Timer2 modulator out-
put 1. The function of the modulator output pin is depend on the Timer2 Mode bits T2M[3..0] bits
in the T2MRB register. The PD5 pin has to be configured as an output (DDD5 set [one]) if the
timer mode is used the output pin to serve this function. When PD5 is not used as modulator out-
put pin, it is a I/O pin.
PCINT21, Pin Change Interrupt Source 21: The PD5 pin can serve as an external interrupt
source.
ECIN1/PCINT20 - Port D, Bit 4
ECIN1: External Clock Input. External system clock input for the clock module on PD4 pin. When
used as a clock pin, the pin can not be used as an I/O pin. The clock will be input if the
CMM[1..0] bits are set (one), the ECINS bit is set (one) and CCS bit is set (one) in the CMCR
register, regardless of the PORTD4 and DDD4 setting, and PORTD4, DDD4 and PIND4 will all
read 0.
PCINT20, Pin Change Interrupt Source 20: The PD4 pin can serve as an external interrupt
source.
INT1/PCINT19 - Port D, Bit 3
INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source.
The pin has to be configured as an input (DDD3 set (zero)) to serve this function.
PCINT19, Pin Change Interrupt Source 19: The PD3 pin can serve as an external interrupt
source.
INT0/PCINT18 - Port D, Bit 2
INT0: External Interrupt source 1. The PD2 pin can serve as an external interrupt source.
The pin has to be configured as an input (DDD2 set (zero)) to serve this function.
PCINT18, Pin Change Interrupt Source 18: The PD2 pin can serve as an external interrupt
source.
相關(guān)PDF資料
PDF描述
A42MX24-2BG100B Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel
A42MX36-2BG100B 40MX and 42MX FPGA Families
A42MX02-2BG100ES Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel
A42MX04-2BG100ES 40MX and 42MX FPGA Families
A42MX09-2BG100ES Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2BG100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2BG100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2BG100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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