- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄352477 > A42MX16-2BG100B (Electronic Theatre Controls, Inc.) 40MX and 42MX FPGA Families PDF資料下載
參數(shù)資料
| 型號(hào)： | A42MX16-2BG100B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 74/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2BG100B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當(dāng)前第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
57
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-23. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between and 1 system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 3-24. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 3-24. Synchronization when Reading a Software Assigned Pin Value
tpd,max
tpd,min
0xFF
0x00
XXX
in r17,PINx
XXX
INSTRUCTIONS
SYNC LATCH
r17
PINxn
SYSTEM CLK
0xFF
0x00
nop
in r17, PINx
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
0xFF
out PORTx, r16
r16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2BG100B | Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel |
| A42MX36-2BG100B | 40MX and 42MX FPGA Families |
| A42MX02-2BG100ES | Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel |
| A42MX04-2BG100ES | 40MX and 42MX FPGA Families |
| A42MX09-2BG100ES | Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:30mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:30mm; Sensor Housing:Barrel |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2BG100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。