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參數(shù)資料
| 型號(hào)： | A42MX16-2BG100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 98/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2BG100A |
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79
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 0 - T0F: Timer0 Flag Bit
When the interval timer in Timer0 generates an output clock pulse (CLK
T0) the T0F bit is set
(one). If the I-bit in SREG and the T0IE bit is set (one) at T0CR the MCU will jump to the corre-
sponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
3.13.4
Timer1
The Timer1 is an interval timer which can be used to generate periodical interrupts and as pres-
caler for Timer2, and Timer3. The Timer1 consists of a programmable 12-bit divider that input
clock (CL1) can be driven by the Timer0 output clock (CLK
T0), I/O clock (CLKI/O), Timer clock
(CLT), the external input clock (T2I) and the external input clock (T3I). The three bits T1CS[2..0]
select the input clock (CL1) for Timer1. The timer output signal can be used as prescaler clock
and as source for the Timer1 interrupt. The interrupt is maskable via the T1IE bit and also the
time interval for the timer output can be adjusted as shown in Figure 3-28 via the T1PS[2..0] bits
in the Timer1 control register T1CR. The timer interrupt flag bit (T1F) is located in the T10IFR
register.
Figure 3-28. Timer1 Block Diagram
T1PS2
T1PS1
T1PS0
CL1
INTT0
12-bit Prescaler
Input
MUX
Output MUX-Timer1
TC1/256
TC1/16
TC1/2
T1C
S
0
T1C
S
1
T1C
S
2
TC1/4
TC1/
8
TC1/
3
2
TC1/1K
TC1/4K
T1IE
CLKT0
CLKI/O
T3I
T2I
CLT
CLKT1
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| A42MX16-2BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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