參數(shù)資料
型號： A42MX16-2BG100A
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 48/120頁
文件大?。?/td> 854K
代理商： A42MX16-2BG100A
33
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Calibrated Internal Low level Slow Frequency RC-oscillator Clock (90 kHz) - SCL
The slow asynchronous Timer clock (SCL) supplies only the Watchdog/Interval Timer. This
allows the Watchdog/Interval Timer to work when the device is in sleep mode.
Calibrated Internal High level Slow Frequency RC-oscillator Clock (90 kHz) - SCH
The slow asynchronous Timer clock (SCH) is a high supply voltage output clock of the slow fre-
quency calibrated internal RC-oscillator (SRC).
3.7.3
Clock Sources
The device has the following clock source options, selectable by the Clock Module Unit. This
special feature of the clock management is capability of switching between these different clock
sources during run time.
3.7.3.1
Default Clock Source
The device is shipped with internal FRC oscillator at 4MHz and with the fuse CKDIV8 pro-
grammed, resulting in 0.5MHz system clock. The startup time is set to maximum and time-out
period enabled. (FRCFS = “0”, SUT = “10”, CKDIV8 = “0”). The default setting ensures that all
users can make their desired clock source setting using any available programming interface.
3.7.3.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start to oscillate and a minimum number of oscillation
cycles before it can be considered as stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. Section 3.9 “System Control and Reset”
on page 41 describes the start conditions for the internal reset. The delay (t
TOUT) is timed from
the SRC - Oscillator and the number of cycles in the delay is set by the SUTx and FRCFS fuse
bits. The selectable delays are shown in Table 3-6. The frequency of the SRC-Oscillator is
depending on whether the calibration data value from the oscillator is loaded to the calibration
register.
Main purpose of the delay is to keep the Atmel
AVR in reset until it is supplied with minimum
V
CC. The delay will not monitor the actual voltage and it will be required to select a delay longer
than the VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit
should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the
time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detec-
tion circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute.
Table 3-6.
Number of SRC – Oscillator Cycles
After Power-on Reset
Typ. Time-out
After all other Resets
Typ. Time-out (VCC = 3.0V)
Number of Cycles
10ms
5.7ms
512
140ms
91ms
8192
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