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參數(shù)資料
| 型號： | A42MX16-2BG100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 17/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2BG100A |
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4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The interconnection between Master and Slave CPU with the SPI is shown in Figure 3-53. The
system consists of two shift registers, and a master clock generator. The SPI master initiates the
communication cycle when pulling low the Slave Select SS - pin of the desired Slave. Master
and Slave prepare the data to be sent in their respective shift Registers, and the Master gener-
ates the required clock pulses on the SCK line to interchange data. Data is always shifted from
Master to Slave on the Master Out - Slave In line or MOSI line, and from Slave to Master on the
Master In, Slave Out or MISO line. After each data package, the Master will synchronize the
Slave by pulling high the Slave Select, SS - line.
When configured as a Master, the SPI interface has no automatic control of the SS - line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF) in the SPI Status Register (SPSR). If the SPI Interrupt Enable bit
(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift
the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select,
SS - line. The last incoming byte will be kept in the Buffer Register for later use. When config-
ured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS -
pin is driven high. In that state, software may update the contents of the SPI Data Register,
SPDR Register, but the data will not be shifted out by incoming clock pulses on the SCK pin until
the SS - pin is driven low. If one byte has been completely shifted, the end of Transmission Flag,
SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is
requested. The Slave may continue to place new data to be sent into SPDR before reading the
incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 3-53. Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register (SPDR)
before the entire shift cycle is completed. When receiving data, however, a received character
must be read from the SPI Data Register before the next character has been completely shifted
in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed f
osc/4.
LSB
SLAVE
MSB
8 Bit Shift Register
LSB
Shift
Enable
MSTR
MASTER
MSB
SS
SCK
SS
SCK
MOSI
MISO
8 Bit Shift Register
SPI
Clock Generator
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2BG100A | 40MX and 42MX FPGA Families |
| A42MX36-2BG100A | 40MX and 42MX FPGA Families |
| A42MX02-2BG100B | 40MX and 42MX FPGA Families |
| A42MX04-2BG100B | 40MX and 42MX FPGA Families |
| A42MX09-2BG100B | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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