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參數(shù)資料
| 型號： | A42MX16-1BG100B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IC CHARGE PUMP FLASH LED 10-MLP |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 34/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-1BG100B |
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4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.6.2
SRAM Data Memory
Figure 3-8 shows how the ATA6289 SRAM Memory is organized. The ATA6289 is a complex
microcontroller with more peripheral units than can be supported within the 64 locations
reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 768
data memory locations address both the Register File, the I/O memory, Extended I/O memory,
and the internal data SRAM. The first 32 locations address the Register File, the next 64 location
the standard I/O memory, then 160 locations of Extended I/O memory, and the next 512 loca-
tions address the internal data SRAM. The five different addressing modes for the data memory
cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with
Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer
registers. The direct addressing reaches the entire data space. The Indirect with Displacement
mode reaches 63 address locations from the base address given by the Y- or Z-register. When
using register indirect addressing modes with automatic pre-decrement and post- increment, the
address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 512bytes of internal data SRAM in the ATA6289 are all accessible through all these
addressing modes. The Register File is described in Section 3.5.4 “General Purpose Register
Figure 3-8.
Data Memory Map
3.6.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two CLK
CPU cycles as described in Figure 3-9 on
0x0000 - 0x001F
0x0020 - 0x005F
0x0100 - 0x02FF
0x0060 - 0x00FF
32 Registers
64 I/O Registers
Internal SRAM
(512 x 8)
160 Ext. I/O Registers
Data Memory
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1BG100ES | Controller IC; Package/Case:16-MLP; Supply Voltage Max:14V; Leaded Process Compatible:Yes; Operating Temp. Max:85 C; Operating Temp. Min:-40 C; Output Voltage Max:6V; Packaging:Cut Tape; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| A42MX16-1BG100I | Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| A42MX16-1BG100M | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| A42MX16-1CQ100 | Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| A42MX16-1CQ100A | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1BG100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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