參數(shù)資料
型號(hào)： A42MX16-1BG100B
廠商： Electronic Theatre Controls, Inc.
英文描述： IC CHARGE PUMP FLASH LED 10-MLP
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 31/120頁
文件大?。?/td> 854K
代理商： A42MX16-1BG100B
18
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
3.5.7.1
Interrupt Response Time
The interrupt execution response for all the enabled Atmel AVR interrupts is four clock cycles
minimum. After four clock cycles the program vector address for the actual interrupt handling
routine is executed. During this four clock cycle periods, the Program Counter is pushed onto
the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock
cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is com-
pleted before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the
interrupt execution response time is increased by four clock cycles. This increase comes in addi-
tion to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Assembly Code Example
inr16, SREG; store SREG value
cli ; disable interrupts during timed sequence
sbiEECR, EEMWE; start EEPROM write
sbiEECR, EEWE
outSREG, r16; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
Assembly Code Example
sei; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
相關(guān)PDF資料
PDF描述
A42MX16-1BG100ES Controller IC; Package/Case:16-MLP; Supply Voltage Max:14V; Leaded Process Compatible:Yes; Operating Temp. Max:85 C; Operating Temp. Min:-40 C; Output Voltage Max:6V; Packaging:Cut Tape; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
A42MX16-1BG100I Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
A42MX16-1BG100M Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
A42MX16-1CQ100 Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No
A42MX16-1CQ100A Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1BG100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1BG100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1BG100M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1CQ100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1CQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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