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參數(shù)資料
| 型號： | A42MX16-1BG100B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IC CHARGE PUMP FLASH LED 10-MLP |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 26/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-1BG100B |
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13
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.5.3
Status Register
The Status Register contains information about the result of the most recently executed arithme-
tic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code. The Status Register
is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt. This must be handled by software.
3.5.3.1
The Atmel AVR Status REGister - SREG - :
Bit 7 - I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I- bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
Bit 6 - T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
Bit 5 - H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See Section 3.22 “Instruction Set Summary” on page 184 for detailed
information.
Bit 4 - S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement
Overflow Flag V. See Section 3.22 “Instruction Set Summary” on page 184 for detailed
information.
Bit 3 - V: Two's Complement Overflow Flag
The Two's Complement Overflow Flag V supports two's complement arithmetic. See Section
3.22 “Instruction Set Summary” on page 184 for detailed information.
Bit 2 - N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See Section
3.22 “Instruction Set Summary” on page 184 for detailed information.
Bit
7
654
321
0
I
T
H
S
V
N
Z
CSREG
Read/Write
R/W
Initial Value
0
000
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1BG100ES | Controller IC; Package/Case:16-MLP; Supply Voltage Max:14V; Leaded Process Compatible:Yes; Operating Temp. Max:85 C; Operating Temp. Min:-40 C; Output Voltage Max:6V; Packaging:Cut Tape; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| A42MX16-1BG100I | Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| A42MX16-1BG100M | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| A42MX16-1CQ100 | Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| A42MX16-1CQ100A | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1BG100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1CQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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