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參數(shù)資料
| 型號： | A42MX16-1BG100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | LED驅(qū)動器 |
| 英文描述： | LED Driver IC; Output Current Max:200mA; Supply Voltage Max:7V; Package/Case:10-MLP; Output Current:200mA; Output Voltage:4.75V; Leaded Process Compatible:Yes; Operating Temp. Max:85 C; Operating Temp. Min:-40 C |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 51/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-1BG100A |
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36
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.7
System Clock Prescaler (CLK)
The Atmel
ATA6289 has a system clock prescaler (Figure 3-14 on page 38), and the system
clock can be divided by setting the CLKPR register, see Section 3.7.8.1 “Clock Prescaler Regis-
ter – CLPR” on page 37. This feature can be used to decrease the system clock frequency and
the power consumption when the requirement for processing power is low. The input clock (CL)
for the prescaler is selectable by the Clock Module Unit, and it will affect the clock frequency of
the CPU and all synchronous peripherals. CLK
I/O, CLKCPU, and CLKFlash are divided by a factor
as shown in Table 3-10 on page 37.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting. The ripple-counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler - even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. To avoid
unintentional changes of clock frequency, a special write procedure must be followed to change
the CLKPS[2..0] bits:
1.
Write the Clock Prescaler Change Enable (CLPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS[2..0] while writing a zero to
CLPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
3.7.8
Timer Clock Prescaler (CLT)
The Atmel ATA6289 has a timer clock prescaler (Figure 3-14 on page 38), and the timer clock
can be divided by setting the CLKPR register, refer to Section 3.7.8.1 “Clock Prescaler Register
– CLPR” on page 37. This feature can be used to decrease the timer clock frequency. The input
clock (CL) for the prescaler is selectable by the Clock Module Unit, and it will affect the clock fre-
quency of the Timers are divided by a factor as shown in Table 3-9 on page 37. When switching
between prescaler settings, the Timer Clock Prescaler ensures that no glitches occur in the
clock system. It also ensures that no intermediate frequency is higher than neither the clock fre-
quency corresponding to the previous setting, nor the clock frequency corresponding to the new
setting. The ripple-counter that implements the prescaler runs at the frequency of the undivided
clock, which may be faster than the Timer's clock frequency. Hence, it is not possible to deter-
mine the state of the prescaler - even if it were readable, and the exact time it takes to switch
from one clock division to the other cannot be exactly predicted. To avoid unintentional changes
of clock frequency, a special write procedure must be followed to change the CLTPS[2..0] bits:
1.
Write the Clock Prescaler Change Enable (CLPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLTPS[2..0] while writing a zero to
CLPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1BG100B | IC CHARGE PUMP FLASH LED 10-MLP |
| A42MX16-1BG100ES | Controller IC; Package/Case:16-MLP; Supply Voltage Max:14V; Leaded Process Compatible:Yes; Operating Temp. Max:85 C; Operating Temp. Min:-40 C; Output Voltage Max:6V; Packaging:Cut Tape; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| A42MX16-1BG100I | Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| A42MX16-1BG100M | Controller IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes |
| A42MX16-1CQ100 | Controller IC; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1BG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1BG100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1CQ100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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