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參數(shù)資料
| 型號(hào)： | A3PE3000-2FG324 |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 141/162頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 324-FBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | ProASIC3E |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 221 |
| 門數(shù)： | 3000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-FBGA（19x19） |
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ProASIC3E Device Family Overview
1-2
Revision 13
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3E FPGAs
do not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Instant On
Flash-based ProASIC3E devices support Level 0 of the Instant On classification standard. This feature
helps in system component initialization, execution of critical tasks before the processor wakes up, setup
and configuration of memory blocks, clock generation, and bus activity management. The Instant On
feature of flash-based ProASIC3E devices greatly simplifies total system design and reduces total
system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these
purposes in a system. In addition, glitches and brownouts in system power will not corrupt the
ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be
reloaded when system power is restored. This enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC3E devices simplify total system design and reduce cost and
design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-based
FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs cannot be
altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and
correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
ProASIC3E devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through an
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design
techniques are used to implement logic and control functions. The combination of fine granularity,
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization
without compromising device routability or performance. Logic functions within the device are
interconnected through a four-level routing hierarchy.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M1A3PE3000-2FGG324 | IC FPGA 1KB FLASH 3M 324-FBGA |
| GSC70DRSN-S273 | CONN EDGECARD 140PS DIP .100 SLD |
| GSC70DRSD-S273 | CONN EDGECARD 140PS DIP .100 SLD |
| ASC50DRTI-S13 | CONN EDGECARD 100POS .100 EXTEND |
| ASC50DREI-S13 | CONN EDGECARD 100POS .100 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PE3000-2FG324I | 功能描述:IC FPGA 1KB FLASH 3M 324-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A3PE3000-2FG484 | 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A3PE3000-2FG484I | 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A3PE3000-2FG484ID | 制造商:Microsemi Corporation 功能描述:FPGA PROASIC3E 3M GATES 310MHZ 130NM 1.5V 484FBGA - Trays |
| A3PE3000-2FG896 | 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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