ProASIC3L DC and Switching Characteristics
2-32
Revision 13
3.3 V PCI-X
Per
PCI-X
spec.
–
High 10
pF
25 4 0.60 2.05 0.04 0.64 0.43 2.09 1.49 2.46 2.74 3.80 3.21 ns
LVDS
24 mA
–
High
–
– 0.60 1.40 0.04 1.23 N/A N/A N/A N/A N/A N/A N/A ns
LVPECL
24 mA
–
High
–
– 0.60 1.38 0.04 1.08 N/A N/A N/A N/A N/A N/A N/A ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
±100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-81 for connectivity. This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-33 Summary of I/O Timing Characteristics—Software Default Settings
–1 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.14 V, Worst Case
VCCI
Advanced I/O Banks
I/O Standard
D
rive
S
tre
ng
th
(mA)
Equiv
.S
o
ft
ware
Default
D
rive
S
tre
ng
th
Op
tio
n
1
Slew
Rate
C
ap
a
citive
L
o
a
d
(pF
)
Ex
tern
al
Re
sistor
(
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
tE
O
U
T
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZL
S
(ns)
t ZH
S
(n
s)
Un
it
s