ProASIC3 Flash Family FPGAs
II
Revision 13
I/Os Per Package 1
ProASIC3
Devices
A3P0152
A3P030
A3P060
A3P125
A3P250 3
A3P400 3
A3P600
A3P1000
Cortex-M1
Devices
M1A3P250 3,5
M1A3P400 3
M1A3P600
M1A3P1000
Package
I/O Type
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
Sing
le-En
d
ed
I/O
4
Di
fferen
tial
I/O
Pairs
QN48
–
34
–
–––
––
QN68
49
–
QN1325
–
818084
87
19
–
CS121
–
96
–
––––
––
VQ100
–
77
71
68
13
–
TQ144
–
91
100
–
––––
––
PQ208
–
133
151
34
151
34
154
35
154
35
FG144
–
96
97
24
972597259725
FG2565,6
–
157
38
178
38
177
43
177
44
FG4846
–
194
38
235
60
300
74
Notes:
to ensure complying with design and board migration requirements.
2. A3P015 is not recommended for new designs.
3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1A3P250 device does not support FG256 or QN132 packages.
6. FG256 and FG484 are footprint-compatible packages.
Table 1 ProASIC3 FPGAs Package Sizes Dimensions
Package
CS121
QN48
QN68
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Length × Width
(mm\mm)
6 × 6
8 × 8
14 × 14
20 × 20
28 × 28
13 × 13
17 × 17
23 × 23
Nominal Area
(mm2)
36
64
196
400
784
169
289
529
Pitch (mm)
0.5
0.4
0.5
1.0
Height (mm)
0.99
0.90
0.75
1.00
1.40
3.40
1.45
1.60
2.23