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參數(shù)資料
| 型號： | A3P125-2VQG100II |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, VQFP-100 |
| 文件頁數(shù)： | 25/49頁 |
| 文件大小： | 5893K |
| 代理商： | A3P125-2VQG100II |
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ProASIC3 DC and Switching Characteristics
2- 104
v1.3
Part Number and Revision Date
Part Number 51700097-002-3
Revised August 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (v1.3)
Page
v1.2
(June 2008)
TJ, Maximum Junction Temperature, was changed to 100° from 110 in the
"Thermal Characteristics" section and EQ 2-2. The calculated result of Maximum
Power Allowed has thus changed to 1.463 W from 1.951 W.
Values for the A3P015 device were added to Table 2-7 Quiescent Supply
Values for the A3P015 device were added to Table 2-14 Different Components
Consumption in ProASIC3 Devices is new.
from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT.
Both fall and rise values were included for tDDRISUD and tDDRIHD in
The typical value for Delay Increments in Programmable Delay Blocks was
changed from 160 to 200 in Table 2-106 ProASIC3 CCC/PLL Specification.
v1.1
(January 2008)
Table note references were added to Table 2-2 Recommended Operating
Conditions 1, and the order of the table notes was changed.
The title for Table 2-4 Overshoot and Undershoot Limits 1 was modified to
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os.
"
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
Table 2-29 I/O Output Buffer Maximum Resistances 1 was revised to include
values for 3.3 V PCI/PCI-X.
updated.
v1.0
(January 2008)
column and was incorrect. It was corrected and changed to TA.
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
The "PLL Behavior at Brownout Condition" section is new.
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
was incorrect. It previously said TJ and it was corrected and changed to TA.
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PDF描述 |
|---|---|
| A3P125-FG144II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144 |
| A3P125-FGG144II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144 |
| A3P125-PQ208II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208 |
| A3P125-PQG208II | FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A3P125-2VQG144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-2VQG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-2VQG144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-2VQG144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| A3P125-DIELOT | 制造商:Microsemi Corporation 功能描述:A3P125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film |
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