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參數(shù)資料
| 型號： | A32400DX-BG313C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2526 CLBS, 40000 GATES, PBGA313 |
| 封裝： | BGA-313 |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 217K |
| 代理商： | A32400DX-BG313C |
12
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
Equation 1.
Power (
W) = C
EQ * VCC
2 * F
(1)
Where:
CEQ is the equivalent capacitance expressed in picofarads
(pF).
VCC is power supply in volts (V).
F is the switching frequency in megahertz (MHz).
Equivalent capacitance is calculated by measuring ICCactive at
a specified frequency and voltage for each circuit component
of interest. Measurements have been made over a range of
frequencies at a fixed value of VCC. Equivalent capacitance is
frequency independent so that the results may be used over a
wide range of operating conditions. Equivalent capacitance
values are shown below.
CEQ Values for Actel FPGAs
Modules (CEQM)
5.2
Input Buffers (CEQI)
11.6
Output Buffers (CEQO)
23.8
Routed Array Clock Buffer Loads (CEQCR)
3.5
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Power = VCC
2 * [(m x C
EQM * f
m)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)
Where:
m
= Number of logic modules switching at frequency
fm
n
= Number of input buffers switching at frequency fn
p
= Number of output buffers switching at frequency
fp
q1
= Number of clock loads on the first routed array
clock
q2
= Number of clock loads on the second routed array
clock
r1
= Fixed capacitance due to first routed array clock
r2
= Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR= Equivalent capacitance of routed array clock in pF
CL
= Output load capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
fq2
= Average second routed array clock rate in MHz
Fixed Capacitance Values for Actel FPGAs
(pF)
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
Device Type
r1
routed_Clk1
r2
routed_Clk2
A3265DX
TBD
A32140DX
TBD
A32200DX
TBD
Logic Modules (m)
= 80% of
combinatorial
modules
Inputs switching (n)
= # of inputs/4
Outputs switching (p)
= # outputs/4
First routed array clock loads (q1)
= 40% of sequential
modules
Second routed array clock loads
(q2)
= 40% of sequential
modules
Load capacitance (CL)
= 35 pF
Average logic module switching
rate (fm)
= F/10
Average input switching rate (fn)
= F/5
Average output switching rate (fp)
= F/10
Average first routed array clock rate
(fq1)
=F
Average second routed array clock
rate (fq2)
= F/2
相關PDF資料 |
PDF描述 |
|---|---|
| A32400DX-BG313I | FPGA, 2526 CLBS, 40000 GATES, PBGA313 |
| A32400DX-PQ240C | FPGA, 2526 CLBS, 40000 GATES, PQFP240 |
| A32400DX-PQ240I | FPGA, 2526 CLBS, 40000 GATES, PQFP240 |
| A32400DX-FRQ240I | FPGA, 5020 CLBS, 40000 GATES, PQFP240 |
| A32400DX-FRQ240M | FPGA, 5020 CLBS, 40000 GATES, PQFP240 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A32400DX-FRQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-FRQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-RQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-RQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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