參數(shù)資料
型號(hào)： A32400DX-BG313C
元件分類： FPGA
英文描述： FPGA, 2526 CLBS, 40000 GATES, PBGA313
封裝： BGA-313
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 217K
代理商： A32400DX-BG313C
21
3200DX Field Programmable Gate Arrays – The System Logic Integrator Family
Predictable Performance:
Tight Delay Distributions
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of inputs
increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
The 3200DX family delivers a very tight fanout delay
distribution. This tight distribution is achieved in two ways:
by decreasing the delay of the interconnect elements and by
decreasing the number of interconnect elements per path.
Actel’s patented PLICE antifuse offers a very low
resistive/capacitive interconnect. The 3200DX family’s
antifuses, fabricated in 0.6 micron lithography, offer nominal
levels of 100 ohms resistance and 7.0 femtofarad (fF)
capacitance per antifuse.
The 3200DX fanout distribution is also tight due to the low
number of antifuses required for each interconnect path. The
3200DX family’s proprietary architecture limits the number
of antifuses per path to a maximum of four, with 90% of
interconnects using two antifuses.
Timing Characteristics
Timing characteristics for 3200DX devices fall into three
categories: family dependent, device dependent, and design
dependent. The input and output buffer characteristics are
common to all 3200DX family members. Internal routing
delays are device dependent. Design dependency means
actual delays are not determined until after placement and
routing of the user’s design is complete. Delay values may
then be determined by using the ALS Timer utility or
performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Since the
3200DX architecture provides deterministic timing and
abundant
routing
resources,
Actel’s
Designer
Series
development tools offers DirectTime; a timing-driven place
and route tool. Using DirectTime, the designer may specify
timing-critical nets and system clock frequency. Using these
timing specifications, the place and route software optimized
the layout of the design to meet the user’s specifications.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns, or
modules.
Long tracks employ three and sometimes four
antifuse
connections.
This
increases
capacitance
and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6% of nets in a
fully utilized device require long tracks. Long tracks
contribute approximately 3 ns to 6 ns delay. This additional
delay is represented statistically in higher fanout (FO=8)
routing delays in the data sheet specifications section.
Timing Derating
A best case timing derating factor of 0.45 is used to reflect
best case processing. Note that this factor is relative to the
“standard speed” timing parameters, and must be multiplied
by the appropriate voltage and temperature derating factors
for a given application.
Timing Derating Factor (Temperature and Voltage)
Timing Derating Factor for Designs at Typical Temperature (T J = 25°C)
and Voltage (5.0 V)
Note:
This derating factor applies to all routing and propagation delays.
Industrial
Military
Min.
Max.
Min.
Max.
(Commercial Specication) x
0.69
1.11
0.67
1.23
(Maximum Specication, Worst-Case Condition) x
0.85
相關(guān)PDF資料
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A32400DX-BG313I FPGA, 2526 CLBS, 40000 GATES, PBGA313
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參數(shù)描述
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A32400DX-FRQ240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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A32400DX-RQ240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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