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參數(shù)資料
| 型號： | A32400DX-BG313C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2526 CLBS, 40000 GATES, PBGA313 |
| 封裝： | BGA-313 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 217K |
| 代理商： | A32400DX-BG313C |
3
3200DX Field Programmable Gate Arrays – The System Logic Integrator Family
Pin Description
CLKA, CLKB
Clock A and Clock B (input)
TTL Clock inputs for clock distribution networks. The Clock
input is buffered prior to clocking the logic modules. This pin
can also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL
Clock
input
for
diagnostic
probe
and
device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground (Input)
Input LOW supply voltage.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, three-state or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O
pins are automatically driven LOW by the ALS software.
MODE
Mode (Input)
The MODE pin controls the use of multi-function pins
(DCLK, PRA, PRB, SDI, TDO). When the MODE pin is
HIGH, the special functions are active.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA/I/O
Probe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin's probe
capabilities
can
be
permanently
disabled
to
protect
programmed design confidentiality. PRA is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB/I/O
Probe B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin is used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities
can
be
permanently
disabled
to
protect
programmed design confidentiality. PRB is active when the
MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
QCLKA/B,C,D Quadrant Clock (Input/Output)
These four pins are the quadrant clock inputs. When not used
as a register control signal, these pins can function as general
purpose I/O.
SDI
Serial Data Input (Input)
Serial
data
input
for
diagnostic
probe
and
device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
TCK
Test Clock
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
TDI
Test Data In
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as
an I/O when the JTAG fuse is not programmed.
TDO
Test Data Out
Serial data output for JTAG instructions and test data. This
pin functions as an I/O when the JTAG fuse is not
programmed.
TMS
Test Mode Select
Serial data input for JTAG test mode. Data is shifted in on the
rising edge of TCLK. This pin functions as an I/O when the
JTAG fuse is not programmed.
VCC
Supply Voltage (Input)
Input HIGH supply voltage.
Note:
TCK, TDI, TDO, TMS are only available on
devices containing JTAG circuitry.
3200DX Architectural Overview
The 3200DX family architecture is composed of fine-grained
building blocks which produce fast, efficient logic designs.
All devices within the 3200DX family are composed of
Logic Modules, Routing Resources, Clock Networks, and I/O
modules which are the building blocks to design fast logic
designs. In addition, a subset of the device family contains
embedded dual-port SRAM modules which can implement
fast SRAM functions such as FIFOs, LIFOs, and scratchpad
memory.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A32400DX-BG313I | FPGA, 2526 CLBS, 40000 GATES, PBGA313 |
| A32400DX-PQ240C | FPGA, 2526 CLBS, 40000 GATES, PQFP240 |
| A32400DX-PQ240I | FPGA, 2526 CLBS, 40000 GATES, PQFP240 |
| A32400DX-FRQ240I | FPGA, 5020 CLBS, 40000 GATES, PQFP240 |
| A32400DX-FRQ240M | FPGA, 5020 CLBS, 40000 GATES, PQFP240 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A32400DX-FRQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-FRQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-RQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-RQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32401-0009 | 功能描述:重負荷電源連接器 A32 PLUG 1/0 AWG RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點數(shù)量: 端接類型:Crimp 觸點材料: 觸點電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型: |
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