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參數(shù)資料
| 型號： | A28F200BR-T |
| 廠商： | Intel Corp. |
| 英文描述： | 2-MBIT (128K x 16) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| 中文描述： | 2兆位（128K的× 16）引導塊閃存（2兆位（128K的× 16）引導塊閃速存儲器） |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 440K |
| 代理商： | A28F200BR-T |
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A28F200BR
E
8
ADVANCE INFORMATION
1.5
Pin Descriptions
Table 1. 28F200 Pin Descriptions
Symbol
Type
Name and Function
A
0
- A
16
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a write cycle.
A
9
INPUT
ADDRESS INPUT:
When A
9
is at V
HH
the signature mode is accessed.
During this mode, A
0
decodes between the manufacturer and device IDs.
When BYTE# is at a logic low, only the lower byte of the signatures are
read. DQ
15
/A
-1
is a don’t care in the signature mode when BYTE# is low.
DQ
0
-DQ
7
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched during the Write cycle. Outputs array, Intelligent
Identifier and Status Register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DQ
8
-DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched during
the Write cycle. Outputs array data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled as in the byte-wide
mode (BYTE# = “0”). In the byte-wide mode DQ
15
/A
-1
becomes the lowest
order address for data output on DQ
0
-DQ
7
.
CE#
INPUT
CHIP ENABLE:
Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby current
will increase due to current flow through the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and array
blocks. WE# is active low. Addresses and data are latched on the rising
edge of the WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses three voltage levels (V
IL
, V
IH
, and
V
HH
) to control two different functions: reset/deep power-down mode and
boot block unlocking. It is backwards-compatible with the 28F200BX/BL.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which puts the outputs at High-Z, resets the Write State Machine,
and draws minimum current.
When RP# is at logic high, the device is in standard operation
. When
RP# transitions from logic-low to logic-high, the device defaults to the
read array mode.
When RP# is at V
HH
, the boot block is unlocked
and can be
programmed or erased. This overides any control from the WP# input.
相關PDF資料 |
PDF描述 |
|---|---|
| A28F200BX-B | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| A28F400BR-B | 4-MBIT (512K x8) Boot Block Flash Memory(4兆位(512K x8) 引導塊閃速存儲器) |
| A28F400BR-T | 4-MBIT (256K x16) Boot Block Flash Memory(4兆位 (256K x16)引導塊閃速存儲器) |
| A28F400BX-B | 4-MBIT (512K x8) Boot Block Flash Memory(4兆位(512K x8) 引導塊閃速存儲器) |
| A6FLR10MS02 | FAST RECOVERY DIODES |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A28F200BR-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BR-T/B |
| A28F200BR-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BX-B - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-T | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BX-T/B |
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