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參數(shù)資料
| 型號： | A23W8308 |
| 英文描述： | 262.144 X 8 BIT CMOS MASK ROM |
| 中文描述： | 262.144 × 8位CMOS掩膜ROM |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 190K |
| 代理商： | A23W8308 |
A23W8308
Preliminary
262,144 X 8 BIT CMOS MASK ROM
PRELIMINARY (November, 1999, Version 0.0)
1
AMIC Technology, Inc.
Features
n
262,144 x 8 bit organization
n
Wide power supply range : +2.7V to +5.5V
n
Access time: 120 ns (max.)/5V
n
150 ns (max.)/3V
n
Current: Operating: 50mA (max.)/5V
15mA (max.)/3V
Standby: 50
μ
A (max.)/5V
25
μ
A (max.)/3V
n
Mask Programmed for Chip Enable (power-down)
CE/
CE
, Output Enable OE/
OE
/NC
n
Three-state outputs for wired-OR expansion
n
Full static operation
n
All inputs and outputs are directly TTL-compatible
n
Available in 32-pin DIP, 32-pin SOP, 32-pin PLCC
packages or in DICE FORM.
General Description
The A23W8308 high-performance Read Only Memory is
configured as 262,144 x 8 bits. It is designed to be
compatible with all microprocessors and similar
applications where high-performance, large-bit storage,
and
simple
interfacing
considerations. This device is designed for use with
operating voltage from 3V to 5V.
are
important
design
The A23W8308 offers an automatic POWER-DOWN
controlled by the Chip Enable CE/
CE
input. When
CE/
CE
goes low/high, the device will automatically
POWER-DOWN and remain in a low power STANDBY
mode as long as CE/
CE
remains low/high. A23W8308
also offers OE/
OE
/NC (Active High or Low or No
Connection), which eliminates bus contention in multiple
bus microprocessor systems.
Pin Configurations
n
P-DIP / SOP
n
PLCC
A23W8308
A6
A10
A9
O
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
O0
O1
O3
O4
O5
A11
A9
A13
VCC
A10
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A8
O2
GND
O6
O7
CE/CE
A14
A5
A4
A3
A2
A1
A0
O0
O7
A8
A13
A14
A
A
A
N
V
N
A
O
O
G
O
O
O
1
2
3
4
5
6
7
8
9
10
11
12
13
3
3
3
1
1
1
1
1
1
221
22
23
24
25
26
27
28
29
OE/OE/NC
18
15
16
17
A0
NC
A17
CE/CE
A11
A7
OE/OE/NC
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