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參數(shù)資料
| 型號： | A1174EEWLT-T |
| 元件分類： | 磁阻傳感器 |
| 英文描述： | MAGNETIC FIELD SENSOR-HALL EFFECT, -5.5-5.5mT, 300mV, RECTANGULAR, SURFACE MOUNT |
| 封裝： | 1.50 X 2 MM, 0.40 MM HEIGHT, LEAD FREE, DFN-6 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 423K |
| 代理商： | A1174EEWLT-T |
Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operating Characteristics Valid over full operating voltage and ambient temperature ranges (unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min.
Typ.1
Max.
Unit
Electrical Characteristics
Supply Voltage2
VDD
TA = 25°C
1.65
–
3.5
V
–40°C ≥ TA ≥ 85°C
1.8
–
3.5
V
Output On Voltage
VOUT(SAT) NMOS on, IOUT = 1 mA
–
100
300
mV
VOUT(HIGH) PMOS on, IOUT = 1 mA
VDD–300 VDD–100
–
mV
Supply Current
IDD(EN)
Chip in awake state (enabled)
–
2.0
mA
IDD(DIS)
Chip in sleep state (disabled)
–
8.0
μA
IDD(AV)
Normal Clock mode, VDD = 2.5 V
–
71
μA
Normal Clock mode, VDD = 3.0 V
–
82
μA
Internal Chopper Stabilization Clock Frequency
fC
–
200
–
kHz
EXTERNAL_CLK and DUAL_CLK Pins Input Current
IIN
VEXTERNAL_CLK=VDD,VDUAL_CLK=VDD
–
0.5
–
mA
EXTERNAL_CLK and DUAL_CLK Pins Leakage Current
IOFF
VEXTERNAL_CLK=0V,VDUAL_CLK=0V
–
0.02
–
μA
Supply Slew Rate3
SR
tOFF = 100 ms
0.1
–
V/ms
Normal Clock Mode Characteristics4
Normal Mode Awake Duration
tawake_norm
–25
38
ms
Normal Mode Period
tperiod_norm
–
0.7
1.05
ms
External Clock Mode Characteristics4
EXTERNAL_CLK and DUAL_CLK Pins Threshold
Vth(HIGH)
–
0.75 × VDD
V
Vth(LOW)
0.25 × VDD
––
V
External Clock Mode Awake Duration
tawake_ext VEXTERNAL_CLK > Vth(HIGH)
38
–
ms
External Clock Mode Period
tperiod_ext VEXTERNAL_CLK > Vth(HIGH)
80
–
ms
State Transition Delay5
tdelay_ext
–25
38
ms
Dual Clock Mode Characteristics4
Dual Clock Mode Awake Duration
tawake_dual
–25
38
ms
Dual Clock Mode Fast Sampling Period
tperiod_fast
–
8 ×
tawake_dual
–ms
Dual Clock Mode Slow Sampling Period
tperiod_slow
–28–
ms
Dual Clock Mode Timeout6
ttimeout
–
100 ×
tperiod_slow
–ms
Magnetic Characteristics2
Operate Point
BOP
South pole to device branded side
5
36
55
G
Release Point
BRP
North pole to device branded side
–55
–36
–5
G
Hysteresis
BHYS
BOP – BRP
–72
110
G
1Typical values are at TA = 25°C and VDD = 2.75 V. Performance may vary for individual units, within the specified maximum and minimum limits.
2Magnetic operate and release points vary with supply voltage.
3If the device power supply is chopped, power-up slew rate dVDD / dt has to be adjusted to ensure correct functioning of the device. tOFF is the time of
the power cycle when VDD < VDD(min).
4Defined in the Functional Description section of this datasheet.
5Time between external clock transition and resulting transition of the device between the awake and sleep states. See Functional Description section.
6If no output transition is detected during the timeout interval, the device goes back into slow sampling. See Functional Description section.
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