- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4435 > A1020B-PQG100I (Microsemi SoC)IC FPGA 2K GATES 100-PQFP IND PDF資料下載
參數(shù)資料
| 型號： | A1020B-PQG100I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 4/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2K GATES 100-PQFP IND |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | ACT™ 1 |
| LAB/CLB數(shù)： | 547 |
| 輸入/輸出數(shù)： | 69 |
| 門數(shù)： | 2000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-PQFP（14x20） |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
12
can be combined with frequency and voltage to represent
active power dissipation.
E qui v a l ent C apac i t ance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
Power (uW) = CEQ * VCC
2 * F
(1)
where:
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a range
of frequencies at a fixed value of VCC. Equivalent capacitance
is frequency independent so that the results can be used over
a wide range of operating conditions. Equivalent capacitance
values are shown below.
CE Q Val ues f o r Act e l FP G A s
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piecewise linear summation
over all components that applies to all ACT 1, 1200XL,
3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has
only one routed array clock, the terms labeled routed_Clk2,
dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2
family has two routed array clocks, and the dedicated_Clk
and IO_Clk terms do not apply. For ACT 3 devices, all terms
will apply.
Power = VCC
2 * [(m * C
EQM* fm)modules + (n * CEQI* fn)inputs +
(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1
+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 +
(r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk +
(s2 * CEQCI * fs2)IO_Clk](2)
where:
CEQ
= Equivalent capacitance in pF
VCC
= Power supply in volts (V)
F
= Switching frequency in MHz
ACT 3
1200XL
3200DX ACT 2 ACT 1
Modules (CEQM)
6.7
5.2
5.8
3.7
Input Buffers (CEQI)
7.2
11.6
12.9
22.1
Output Buffers (CEQO)
10.4
23.8
31.2
Routed Array Clock
Buffer Loads (CEQCR)
1.6
3.5
3.9
4.6
Dedicated Clock Buffer
Loads (CEQCD)
0.7
N/A
I/O Clock Buffer Loads
(CEQCI)
0.9
N/A
m
= Number of logic modules switching at fm
n
= Number of input buffers switching at fn
p
= Number of output buffers switching at fp
q1
= Number of clock loads on the first routed
array clock (all families)
q2
= Number of clock loads on the second routed
array clock (ACT 2, 1200XL, 3200DX, ACT 3
only)
r1
= Fixed capacitance due to first routed array
clock (all families)
r2
= Fixed capacitance due to second routed array
clock (ACT 2, 1200XL, 3200DX, ACT 3 only)
s1
= Fixed number of clock loads on the dedicated
array clock (ACT 3 only)
s2
= Fixed number of clock loads on the dedicated
I/O clock (ACT 3 only)
CEQM
= Equivalent capacitance of logic modules in pF
CEQI
= Equivalent capacitance of input buffers in pF
CEQO
= Equivalent capacitance of output buffers
in pF
CEQCR
= Equivalent capacitance of routed array clock
in pF
CEQCD
= Equivalent capacitance of dedicated array
clock in pF
CEQCI
= Equivalent capacitance of dedicated I/O clock
in pF
CL
= Output lead capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
(all families)
fq2
= Average second routed array clock rate in
MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)
fs1
= Average dedicated array clock rate in MHz
(ACT 3 only)
fs2
= Average dedicated I/O clock rate in MHz
(ACT 3 only)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP20K100EQC240-2X | IC APEX 20KE FPGA 100K 240-PQFP |
| HMC49DREI-S13 | CONN EDGECARD 98POS .100 EXTEND |
| A54SX32A-2TQG176I | IC FPGA SX 48K GATES 176-TQFP |
| A54SX32A-2TQ176I | IC FPGA SX 48K GATES 176-TQFP |
| ACC49DRTS-S13 | CONN EDGECARD 98POS .100 EXTEND |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1020BSB1 | 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:EDGE CARD IDC TYPE (REINFORCED TYPE) |
| A1020BSB2 | 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:EDGE CARD IDC TYPE (REINFORCED TYPE) |
| A1020BSD1 | 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:EDGE CARD IDC TYPE (REINFORCED TYPE) |
| A1020BSD2 | 制造商:DBLECTRO 制造商全稱:DB Lectro Inc 功能描述:EDGE CARD IDC TYPE (REINFORCED TYPE) |
| A1020B-STDCQ84B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。