參數(shù)資料
型號： 9S12XDP512DGV1
英文描述： Device User Guide for Mask Set 0L40V ( First Silicon)
中文描述： 設備用戶指南掩模組0L40V（第一硅）
文件頁數(shù)： 90/152頁
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV1
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
90
The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of
the
RESET
signal in Emulation Expanded Mode, Emulation Single Chip Mode and Normal Expanded
Mode.(
Table 4-2
) The state of the EROMCTL pin is latched into the EROMON bit in the MISC register
on the rising edge of the
RESET
signal in Emulation Expanded Mode or Emulation Single Chip
Mode(
Table 4-4
).
Table 4-3 EROMON Pin Control Function
Mode
PE3 = EROMCTL
Special Single Chip Mode
4.2.3 Oscillator Configuration Pin Control
At reset the configuration of the Oscillator can be selected using the XCLKS pin. The state of this pin on
the rising edge of the RESET pin determines which oscillator will be used.
Table 4-2 ROMON Pin Control Function
Mode
PK7 = ROMCTL
X
0
1
X
0
1
X
0
1
ROMON Bit
1
0
1
0
0
1
1
0
1
Special Single Chip Mode
Emulation Expanded Mode
Special Test Mode
Emulation Single Chip Mode
Normal Single Chip Mode
Normal Expanded Mode
EROMON Bit
0
0
1
0
0
1
0
0
1
X
0
1
X
0
1
X
0
1
Emulation Expanded Mode
Special Test Mode
Emulation Single Chip Mode
Normal Single Chip Mode
Normal Expanded Mode
Table 4-4 Clock Selection Based on PE7
PE7 = XCLKS
Description
0
Full swing pierce oscillator or external clock source selected
1
Loop controlled pierce oscillator selected
F
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料
PDF描述
9S12XDP512DGV2 Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
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相關代理商/技術參數(shù)
參數(shù)描述
9S12XDP512DGV2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
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