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| 型號(hào)： | 9S12DP256BDGV2 |
| 英文描述： | 9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
| 中文描述： | 9S12Dx256B設(shè)備指南。也包括C衍生物和9S12Ax256設(shè)備 |
| 文件頁(yè)數(shù)： | 95/126頁(yè) |
| 文件大?。?/td> | 1809K |
| 代理商： | 9S12DP256BDGV2 |
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MC9S12DJ64 Device User Guide — V01.17
95
A.2 ATD Characteristics
This section describes the characteristics of the analog to digital converter.
A.2.1 ATD Operating Characteristics
The
Table A-8
shows conditions under which the ATD operates.
The following constraints exist to obtain full-scale, full range results:
V
SSA
≤
V
RL
≤
V
IN
≤
V
RH
≤
V
DDA
.
This constraint exists since the sample buffer amplifier can not drive
beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively
be clipped.
Table A-8 ATD Operating Characteristics
A.2.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.2.2.1 Source Resistance:
Due to the input pin leakage current as specified in
Table A-6
in conjunction with the source resistance
there will be a voltage drop from the signal source to the ATD input. The maximum source resistance R
S
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D
Reference Potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
4.50
V
DDA
/2
V
DDA
5.25
V
V
2
C Differential Reference Voltage
1
NOTES
:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50V
2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
V
RH
-V
RL
f
ATDCLK
5.00
V
3
D ATD Clock Frequency
0.5
2.0
MHz
4
D
ATD 10-Bit Conversion Period
Clock Cycles
2
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV10
T
CONV10
14
7
28
14
Cycles
μ
s
5
D
ATD 8-Bit Conversion Period
Clock Cycles
2
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV8
T
CONV8
12
6
26
13
Cycles
μ
s
6
D Recovery Time (V
DDA
=5.0 Volts)
t
REC
I
REF
I
REF
20
μ
s
7
P Reference Supply current 2 ATD blocks on
0.750
mA
8
P Reference Supply current 1 ATD block on
0.375
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9S12DP512DGV1 | 9S12Dx512 Device Guide |
| 9S12DT128BDGV1 | 9S12DT128B Device Guide |
| 9S12DT128DGV2 | MC9S12DT128 Device User Guide V02.09 |
| 9S12DT128DGV2D | MC9S12DT128 Device User Guide V02.09 |
| 9S12DT256DGV3 | MC9S12DT256 Device User Guide V03.03 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9S12DP512DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx512 Device Guide |
| 9S12DT128BDGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DT128B Device Guide |
| 9S12DT128DGV2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MC9S12DT128 Device User Guide V02.09 |
| 9S12DT128DGV2D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MC9S12DT128 Device User Guide V02.09 |
| 9S12DT256DGV3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MC9S12DT256 Device User Guide V03.03 |
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