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參數(shù)資料
| 型號： | 9S12DP256BDGV2 |
| 英文描述： | 9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
| 中文描述： | 9S12Dx256B設(shè)備指南。也包括C衍生物和9S12Ax256設(shè)備 |
| 文件頁數(shù)： | 63/126頁 |
| 文件大小： | 1809K |
| 代理商： | 9S12DP256BDGV2 |
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MC9S12DJ64 Device User Guide — V01.17
63
2.4.1 VDDX, VSSX — Power & Ground Pins for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
currentdemandsonthepowersupply,usebypasscapacitorswithhigh-frequencycharacteristicsandplace
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded.
VDDX and VSSX are the supplies for Ports J, K, M, P, T and S.
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal
Voltage Regulator
External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded.
VDDR and VSSR are the supplies for Ports A, B, E and H.
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins
Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the
internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is
turned off, if VREGEN is tied to ground.
NOTE:
No load allowed except for bypass capacitors.
2.4.4 VDDA, VSSA — Power Supply Pins for ATD0/ATD1 and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the two analog to
digital converters. It also provides the reference for the internal voltage regulator. This allows the supply
voltage to ATD0/ATD1 and the reference voltage to be bypassed independently.
VDDPLL
43
2.5V
Provides operating voltage and ground for the Phased-Locked
Loop. This allows the supply voltage to the PLL to be
bypassed independently. Internal power and ground
generated by internal regulator.
Internal Voltage Regulator enable/disable
VSSPLL
45
0V
VREGEN
97
5.0V
Mnemonic
Pin Number
112-pin QFP
Nominal
Voltage
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9S12DP512DGV1 | 9S12Dx512 Device Guide |
| 9S12DT128BDGV1 | 9S12DT128B Device Guide |
| 9S12DT128DGV2 | MC9S12DT128 Device User Guide V02.09 |
| 9S12DT128DGV2D | MC9S12DT128 Device User Guide V02.09 |
| 9S12DT256DGV3 | MC9S12DT256 Device User Guide V03.03 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9S12DP512DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx512 Device Guide |
| 9S12DT128BDGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DT128B Device Guide |
| 9S12DT128DGV2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MC9S12DT128 Device User Guide V02.09 |
| 9S12DT128DGV2D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MC9S12DT128 Device User Guide V02.09 |
| 9S12DT256DGV3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:MC9S12DT256 Device User Guide V03.03 |
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