參數(shù)資料
型號(hào): 9FG1901HKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MLF-72
文件頁數(shù): 11/18頁
文件大?。?/td> 245K
代理商: 9FG1901HKLFT
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
2
Pin Configuration
72-pin MLF
Power Down Functionality
Functionality at Power Up (PLL Mode)
Power Groups
VDDA/PD#
CLK_IN/CLK_IN#
DIF
DIF#
3.3V (NOM)
Running
ON
GND
X
OFF
Functionality Note
It is recommended that Byte 2, bit 6 be toggled from 1 to 0
and back to 1, the first time VDDA is applied. This ensures
proper initialization of the device.
Hi-Z
INPUTS
OUTPUTS
PLL State
Running
FS_A_410
1
CLK_IN
(CPU FSB)
MHz
DIF(18:0)
MHz
1
100 <= CLK_IN < 200
CLK_IN
0
200<= CLK_IN <= 400
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the V
IL_FS
and V
IH_FS specifications in the Input/Supply/Common Output
Parameters Table for correct values.
VDD
GND
3
2
Main PLL, Analog
11,27,47,63 10,28,46,64
DIF clocks
Description
Pin Number
S
M
B
_
A
2_P
LLB
Y
P
#
CLK
_
IN
#
CLK
_
IN
O
E
17_18#
DI
F
_18
#
DI
F
_18
DI
F
_17
#
DI
F
_17
GN
D
VD
D
DI
F
_16
#
DI
F
_16
O
E
16#
DI
F
_15
#
DI
F
_15
O
E
15#
DI
F
_14
#
DI
F
_14
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF
1
54 OE14#
GNDA
2
53 DIF_13#
VDDA/PD#
3
52 DIF_13
HIGH_BW#
4
51 OE13#
FS_A_410
5
50 DIF_12#
DIF_0
6
49 DIF_12
DIF_0#
7
48 OE12#
DIF_1
8
47 VDD
DIF_1#
9
46 GND
GND 10
45 DIF_11#
VDD 11
44 DIF_11
DIF_2 12
43 OE11#
DIF_2# 13
42 DIF_10#
DIF_3 14
41 DIF_10
DIF_3# 15
40 OE10#
DIF_4 16
39 DIF_9#
DIF_4# 17
38 DIF_9
OE_01234# 18
37 OE9#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SM
BC
L
K
SM
BD
AT
OE
5
#
DI
F
_
5
DI
F
_5#
OE
6
#
DI
F
_
6
DI
F
_6#
VD
D
GN
D
OE
7
#
DI
F
_
7
DI
F
_7#
OE
8
#
DI
F
_
8
DI
F
_8#
SM
B_
A
0
SM
B_
A
1
9FG1901
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