參數(shù)資料
型號(hào): 9FG1901HKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MLF-72
文件頁數(shù): 1/18頁
文件大小: 245K
代理商: 9FG1901HKLFT
9FG1901H
IDTTM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
DATASHEET
1
Description
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
Key Specifications
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Features/Benefits
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
VDDA controlled power down mode
Funtional Block Diagram
STOP
LOGIC
CLK_IN
CLK_IN#
DIF(16:0)
CONTROL
LOGIC
HIGH_BW#
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
17
IREF
OE(16:5)#,
OE_01234#
13
SMB_A0
SMB_A1
FS_A_410
STOP
LOGIC
DIF(18:17)
2
OE_17_18#
GEAR
SHIFT
LOGIC
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
相關(guān)PDF資料
PDF描述
9FG1901YKLF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
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