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參數(shù)資料
| 型號： | 9EX21801AKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, PQCC72 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-72 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 160K |
| 代理商： | 9EX21801AKLFT |
IDTTM
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463B — 01/20/10
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
11
Datasheet
SMBusTable: Output, and PLL BW Control Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
RW
Latch
Bit 6
RW
Latch
Bit 5
DIF_17
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_16
Output Control
RW
Hi-Z
Enable
1
Bit 3
0
Bit 2
100M_133M#
Frequency Select Bit C
RW
133MHz
100MHz
Latch
Bit 1
FSB
Frequency Select Bit B
RW
0
Bit 0
FSA
Frequency Select bit A
RW
1
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
DIF_7
Output Control
RW
Hi-Z
Enable
1
Bit 6
DIF_6
Output Control
RW
Hi-Z
Enable
1
Bit 5
DIF_5
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_4
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_3
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_2
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_1
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_0
Output Control
RW
Hi-Z
Enable
1
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
DIF_15
Output Control
RW
Hi-Z
Enable
1
Bit 6
DIF_14
Output Control
RW
Hi-Z
Enable
1
Bit 5
DIF_13
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_12
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_11
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_10
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_9
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_8
Output Control
RW
Hi-Z
Enable
1
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type0
1PWD
Bit 7
OE11# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 6
OE10# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 5
OE9# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 4
OE8# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 3
OE7# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 2
OE6# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 1
OE5# Input
Pin Readback
R
Pin Low
Pin Hi
X
Bit 0
OE_01234# Input
Pin Readback
R
Pin Low
Pin Hi
X
00 = Low BW (1MHz)
10 = Bypass
11 = High BW (3MHz)
See Frequency Select
Table
Byte 3
72
36
52
49
59
56
2
5
PLL_BW# adjust
BYPASS# test mode / PLL
-
4
-
Byte 1
Byte 2
Byte 0
RESERVED
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PDF描述 |
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| 9FG104DGLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9EX21831AKLF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9EX21831AKLFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9EZCA0100000000 | 制造商:Eaton Corporation 功能描述:9E 20 & 30 kVA IAC - Tie for 1+1 Redundant with Maintenance Bypass |
| 9F-110 | 制造商:NA 功能描述: |
| 9F33U0 | 制造商:Thomas & Betts 功能描述:30A,PLG,REV,3P3W,DG,U0,600VAC, |
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