參數(shù)資料
型號： 9EX21801AKLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： PLL BASED CLOCK DRIVER, PQCC72
封裝： ROHS COMPLIANT, PLASTIC, MLF-72
文件頁數(shù)： 8/14頁
文件大?。?/td> 160K
代理商： 9EX21801AKLF
IDTTM
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463B — 01/20/10
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
3
Datasheet
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
VDD
PWR
Power supply, nominal 3.3V
2OE10#
IN
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
3
DIF_10
OUT
0.7V differential true clock output
4
DIF_10#
OUT
0.7V differential complement clock output
5OE11#
IN
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
6
DIF_11
OUT
0.7V differential true clock output
7
DIF_11#
OUT
0.7V differential complement clock output
8OE12#
IN
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
9
DIF_12
OUT
0.7V differential true clock output
10
DIF_12#
OUT
0.7V differential complement clock output
11
GND
PWR
Ground pin.
12
VDD
PWR
Power supply, nominal 3.3V
13
DIF_13
OUT
0.7V differential true clock output
14
DIF_13#
OUT
0.7V differential complement clock output
15
OE13#
IN
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
16
DIF_14
OUT
0.7V differential true clock output
17
DIF_14#
OUT
0.7V differential complement clock output
18
OE14#
IN
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
19
DIF_15
OUT
0.7V differential true clock output
20
DIF_15#
OUT
0.7V differential complement clock output
21
VDD
PWR
Power supply, nominal 3.3V
22
OE15_17#
IN
Active low input for enabling DIF pairs 15, 16 and 17
1 = tri-state outputs, 0 = enable outputs
23
DIF_16
OUT
0.7V differential true clock output
24
DIF_16#
OUT
0.7V differential complement clock output
25
DIF_17
OUT
0.7V differential true clock output
26
DIF_17#
OUT
0.7V differential complement clock output
27
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475
ohms is the standard value.
28
GNDA
PWR
Ground pin for the PLL core.
29
VDDA
PWR
3.3V power for the PLL core.
30
CLKA_IN
IN
True Input for differential reference clock.
31
CLKA_IN#
IN
Complement Input for differential reference clock.
32
GND
PWR
Ground pin.
33
CLKB_IN
IN
True Input for differential reference clock.
34
CLKB_IN#
IN
Complement Input for differential reference clock.
35
VDD
PWR
Power supply, nominal 3.3V
36
OE_01234#
IN
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
相關(guān)PDF資料
PDF描述
9EX21801AKLFT PLL BASED CLOCK DRIVER, PQCC72
9EX21831AKLFT 21831 SERIES, PLL BASED CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9EX21801AKLFT 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9EX21831AKLF 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
9EX21831AKLFT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
9EZCA0100000000 制造商:Eaton Corporation 功能描述:9E 20 & 30 kVA IAC - Tie for 1+1 Redundant with Maintenance Bypass
9F-110 制造商:NA 功能描述:
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