參數(shù)資料
型號(hào): 9EX21801AKLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: PLL BASED CLOCK DRIVER, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù): 13/14頁(yè)
文件大?。?/td> 160K
代理商: 9EX21801AKLF
IDTTM
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
1463B — 01/20/10
ICS9EX21801A
18 Output PCIe G2/QPI Differential Buffer with 2:1 input mux
8
Datasheet
Electrical Characteristics - Phase Jitter (PLL Mode)
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP.
MAX
UNITS
NOTES
PLL Bandwidth
BWH
High Bandwidth Selected
2
3
4
MHz
PLL Bandwidth
BWL
Low Bandwidth Selected
0.7
1
2
MHz
PLL Jitter Peaking
jPKH
High Bandwidth Selected
2.5
3
dB
PLL Jitter Peaking
jPKL
Low Bandwidth Selected
2
2.5
dB
PCIe Gen 1
(1.5 - 22 MHz)
36/42
108
ps
1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Lo-band content (10kHz to 1.5MHz)
1.1/1.2
3
ps rms
1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Hi-band content (1.5MHz to Nyquist)
2.0/2.1
3.1
ps rms
1,2
QPI_133MHz (4.8Gb, 12 UI)
0.24/0.25
0.5
ps rms
2, 3
QPI_133MHz (6.4Gb, 12 UI)
0.18/0.19
0.5
ps rms
2, 3
PCIe Gen 1
(1.5 - 22 MHz)
28/32
86
ps
1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Lo-band content (10kHz to 1.5MHz)
1.2/1.5
3
ps rms
1,2
PCIe Gen 2
(8-16 MHz, 5-16 MHz)
Hi-band content (1.5MHz to Nyquist)
2.6/2.7
3.1
ps rms
1,2
QPI_133MHz (4.8Gb, 12 UI)
0.27/0.28
0.5
ps rms
2, 3
QPI_133MHz (6.4Gb, 12 UI)
0.2/0.21
0.5
ps rms
2, 3
Notes on Phase Jitter: (Guaranteed by design and characterization, not tested in production)
1 See http://www.pcisig.com for complete specs. First number is Spread Spectrum Off, second is Spread Spectrum On.
2 Device driven by IDT CK410B+ (932S421CGLF) or CK509B (932S509EKLF) or equivalent
3 Calculated from Intel Supplied Clock Jitter Tool 1.5.1. First number is Spread Spectrum Off, second is Spread Spectrum On
Jitter, Phase
tjphase_LoBW
tjphase_HIBW
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