參數(shù)資料
型號: 9EPRS475CGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁數(shù): 9/20頁
文件大小: 177K
代理商: 9EPRS475CGLF
IDT
System Clock for Embedded AMDTM based Systems
1615B—04/26/10
9EPRS475
System Clock for Embedded AMDTM based Systems
17
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
33.33MHz output nominal
29.9910
30.0090
ns
2
33.33MHz output spread
29.9910
30.1598
ns
2
66.67MHz output nominal
14.9955
15.0045
ns
2
66.67MHz output spread
14.9955
15.0799
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
1
V OH @MIN = 1.0 V
-33
mA
1
VOH@ MAX = 3.135 V
-33
mA
1
VOL @ MIN = 1.95 V
30
mA
1
VOL @ MAX = 0.4 V
38
mA
1
Edge Rate
δV/δt
Rising edge rate
(VOL = 0.4 V, VOH = 2.4 V)
14
V/ns
1
Edge Rate
δV/δt
Falling edge rate
(VOL = 0.4 V, VOH = 2.4 V)
14
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
180
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22
(unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz
IOH
Electrical Characteristics - Single-ended HTT 66MHz Clock
IOL
Output Low Current
PCI33 Clock period
HTT66 Clock period
Tperiod
Output High Current
AC Electrical Characteristics - Low-Power DIF Outputs: SRC, SB_SRC, ATIG
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Rising Edge Slew Rate
t
SLR
Differential Measurement
0.6
4
V/ns
1,2
Falling Edge Slew Rate
t
FLR
Differential Measurement
0.6
4
V/ns
1,2
Slew Rate Variation
t
SLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
V
HIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
V
LOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
V
SWING
Differential Measurement
300
mV
1
Crossing Point Voltage
V
XABS
Single-ended Measurement
300
550
mV
1,3,4
Crossing Point Variation
V
XABSVAR
Single-ended Measurement
140
mV
1,3,5
Duty Cycle
D
CYC
Differential Measurement
45
55
%
1
SRC Jitter - Cycle to Cycle
SRCJ
C2C
Differential Measurement
125
ps
1
SRC[3:0] Skew
SRC
SKEW
Differential Measurement
100
ps
1
SB_SRC[1:0] Skew
SRC
SKEW
Differential Measurement
100
ps
1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
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