參數(shù)資料
型號(hào): 9EPRS475CGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁(yè)數(shù): 19/20頁(yè)
文件大?。?/td> 177K
代理商: 9EPRS475CGLF
IDT
System Clock for Embedded AMDTM based Systems
1615B—04/26/10
9EPRS475
System Clock for Embedded AMDTM based Systems
8
SMBus Table: Latched Input Readback Output Enable Control Register
Byte
0
Name
Description
X.3
0
1
Default
Bit 7
SEL_HTT66 readback
Hypertransport Select
R
100MHz Differential HTT
clock
66 MHz 3.3V Single-
ended HTT clock
Latch
Bit 6
0
Bit 5
REF0_OE
Output Enable
RW
Low
Enabled
1
Bit 4
REF1_OE
Output Enable
RW
Low
Enabled
1
Bit 3
REF2_OE
Output Enable
RW
Low
Enabled
1
Bit 2
48MHz_1_OE
Output Enable
RW
Low
Enabled
1
Bit 1
48MHz_0_OE
Output Enable
RW
Low
Enabled
1
Bit 0
SS_Enable
Spread Spectrum Enable
(CPU, HTT)
RW
Spread Off
Spread On
0
SMBus Table:Output Enable Control Register
Byte
1
Name
Control Function
Type
0
1
Default
Bit 7
CPU1_OE
Output enable
RW
Low/Low
Enable
1
Bit 6
CPU0_OE
Output enable
RW
Low/Low
Enable
1
Bit 5
SRC3_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 4
SRC2_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 3
HTT100_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 2
SRC1_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 1
1
Bit 0
SRC0_OE
Output Enable
RW
Low/Low
Enabled
1
SMBus Table: Output Enable and 48MHz Strength Control Register
Byte
2
Name
Control Function
Type
0
1
Default
Bit 7
SB_SRC1_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 6
SB_SRC0_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 5
SRC_PLL_SS_Enable
Spread Spectrum Enable (SRC,
SB_SRC, ATIG)
RW
Spread Off
Spread On
0
Bit 4
ATIG2_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 3
ATIG1_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 2
ATIG0_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 1
48MHz_1_Strength
48MHz_1 Drive Strength Sel.
RW
1 Load
2 Load
1
Bit 0
48MHz_0_Strength
48MHz_0 Drive Strength Sel.
RW
1 Load
2 Load
1
SMBus Table: CPU/HTT Frequency Control Register
Byte
3
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
CPU_FS4
CPU Frequency Select MSB
RW
0
Bit 3
CPU_FS3
CPU Frequency Select
RW
1
Bit 2
CPU_FS2
CPU Frequency Select
RW
1
Bit 1
CPU_FS1
CPU Frequency Select
RW
1
Bit 0
CPU_FS0
CPU Frequency Select LSB
RW
1
SMBus Table: SRC Frequency Control Register
Byte
4
Name
Control Function
Type
0
1
Default
Bit 7
REF0_Strength
REF0_Drive Strength Sel
RW
1 Load
2 Load
1
Bit 6
REF1_Strength
REF1_Drive Strength Sel
RW
1 Load
2 Load
1
Bit 5
REF2_Strength
REF2_Drive Strength Sel
RW
1 Load
2 Load
1
Bit 4
SRC_FS4
SRC Frequency Select MSB
RW
0
Bit 3
SRC_FS3
SRC Frequency Select
RW
1
Bit 2
SRC_FS2
SRC Frequency Select
RW
1
Bit 1
SRC_FS1
SRC Frequency Select
RW
1
Bit 0
SRC_FS0
SRC Frequency Select LSB
RW
1
Reserved
See CPU Frequency Select Table
Default value corresponds to 200MHz.
Note that Selected HTT frequency tracks the
CPU frequency.
See SRC Frequency Select Table
Note: SB_SRC and ATIG Clocks are
synchronous to these outputs. Changing this
frequency will alter the SB_SRC and ATIG
frequency by the same percentage.
Reserved
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9EPRS488CKLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Embedded 72P CLK f/ AMD Based System RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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