IDTTM
Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
9
I
2C Table: Spread Spectrum Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
SSP13
RW
-
X
Bit 4
SSP12
RW
-
X
Bit 3
SSP11
RW
-
X
Bit 2
SSP10
RW
-
X
Bit 1
SSP9
RW
-
X
Bit 0
SSP8
RW
-
X
I
2C Table: Output Divider Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC Div3
RW
X
Bit 6
SRC Div2
RW
X
Bit 5
SRC Div1
RW
X
Bit 4
SRC Div0
RW
X
Bit 3
CPU Div3
RW
X
Bit 2
CPU Div2
RW
X
Bit 1
CPU Div1
RW
X
Bit 0
CPU Div0
RW
X
I
2C Table: Output Divider Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
PCI Div3
RW
X
Bit 2
PCI Div2
RW
X
Bit 1
PCI Div1
RW
X
Bit 0
PCI Div0
RW
X
I
2C Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
PCIINV
PCI Phase Invert
RW
Default
Inverse
0
Bit 5
SRCINV
SRC Phase Invert
RW
Default
Inverse
0
Bit 4
CPUINV
CPU Phase Invert
RW
Default
Inverse
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
I
2C Table: Group Skew Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_Skw3
RW
0
Bit 6
SRC_Skw2
RW
0
Bit 5
SRC_Skw1
RW
0
Bit 4
SRC_Skw0
RW
0
Bit 3
CPU_Skw3
RW
0
Bit 2
CPU_Skw2
RW
0
Bit 1
CPU_Skw1
RW
0
Bit 0
CPU_Skw0
RW
0
SRC Skew Control
CPU Skew Control
-
It is recommended
to use ICS Spread
% table for spread
programming.
Byte 14
-
Byte 15
-
SRC divider ratio
can be configured
via these 4 bits
individually.
-
CPU divider ratio
can be configured
via these 4 bits
individually.
-
Byte 16
-
PCI divider ratio
can be configured
via these 4 bits
individually.
-
See Table: Divider Ratio
Combination Table
Byte 18
Byte 17
-
See Table: 7-Steps Skew
Programming Table
See Table: 7-Steps Skew
Programming Table
-
RESERVED
See Table: Divider Ratio
Combination Table
See Table: Divider Ratio
Combination Table
RESERVED