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參數(shù)資料
| 型號： | 9E4101YFILFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO56 |
| 封裝： | 0.300 INCH, 0.250 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 188K |
| 代理商： | 9E4101YFILFT |
IDTTM
Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
3
Pin Description (continued)
Pin #
PIN NAME
TYPE
DESCRIPTION
29
GND
PWR
Ground pin.
30
SRCCLKC5
OUT
Complement clock of differential SRC clock pair.
31
SRCCLKT5
OUT
True clock of differential SRC clock pair.
32
SRCCLKC6
OUT
Complement clock of differential SRC clock pair.
33
SRCCLKT6
OUT
True clock of differential SRC clock pair.
34
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
35
CPUCLKC2_ITP/SRCCLKC_7
OUT
Complimentary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are
required for voltage bias. Selected by ITP_EN input.
36
CPUCLKT2_ITP/SRCCLKT_7
OUT
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output.
These are current mode outputs. External resistors are required for
voltage bias. Selected by ITP_EN input.
37
VDDA
PWR
3.3V power for the PLL core.
38
GNDA
PWR
Ground pin for the PLL core.
39
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
40
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
41
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
44
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
47
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
48
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
49
X2
OUT
Crystal output, Nominally 14.318MHz
50
X1
IN
Crystal input, Nominally 14.318MHz.
51
GND
PWR
Ground pin.
52
REFOUT
OUT
Reference Clock output
53
FS_C/TEST_SEL
IN
3.3V tolerant input for CPU frequency selection. Low voltage
threshold inputs, see input electrical characteristics for Vil_FS and
Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
54
PCICLK0
OUT
PCI clock output.
55
PCICLK1
OUT
PCI clock output.
56
PCICLK2
OUT
PCI clock output.
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