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參數(shù)資料
| 型號(hào)： | 9DB423BFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | 9DB423BFLF |
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9DB423B
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
19
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Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
IDT Singapore Pte. Ltd.
1 Kallang Sector #07-01/06
KolamAyer Industrial Park
Singapore 349276
Phone: 65-6-744-3356
Fax: 65-6-744-1764
Europe
IDT Europe Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU England
Phone: 44-1372-363339
Fax: 44-1372-378851
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
Revision History
Rev.
Issue Date Description
Page #
A
9/30/2008
1. Updated Electrical Characteristics to add propagation delay and phase noise information.
2. Corrected SMBus to reference pin numbers for 423 instead of 823 device.
3. Removed references to OE controls that are not present on 423.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus interface to work
6. Added foot note to Byte 1 about functionality of OE bits and OE pins.
7. Corrected Block Diagram with proper OE pins indicated and PD and DIF_STOP# pins
added
8. Updated clock periods to reflect +/-100ppm input clock tolerance
(CK410B+/CK420BQ/CK505).
9. Changed SRC_Stop references to DIF_Stop references for consistency.
Various
B
2/3/2010
1. Corrected Polarity of PD pin when OE_INV = 1. PD is always active low (or PD#). This is
a difference from the 9DB803D.
Various
C
1/27/2011
Updated Termination Figure 4
10
D
5/9/2011
1. Update pin 1 pin-name and pin description from VDD to VDDR. This highlights that
optimal peformance is obtained by treating VDDR as in analog pin. This is a document
update only, there is no silicon change.
Various
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB423BFLFT | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| 9DB423BGLF | 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB423BGLFT | 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB433AFILF | 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB433AFILFT | 功能描述:時(shí)鐘緩沖器 4 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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