- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25564 > 9DB306BL (INTEGRATED DEVICE TECHNOLOGY INC) 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 PDF資料下載
參數(shù)資料
| 型號： | 9DB306BL |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 4.40 X 9.70 MM, 0.925 MM HEIGHT, TSSOP-28 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 268K |
| 代理商： | 9DB306BL |
ICS9DB306BL REVISION C AUGUST 13, 2009
9
2009 Integrated Device Technology, Inc.
ICS9DB306 Data Sheet
PCI EXPRESS JITTER ATTENUATOR
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are de-
signed to drive 50
Ω transmission lines. Matched impedance
techniques should be used to maximize operating frequency
and minimize signal distortion.
Figures 4A and 4B show two
different layouts which are recommended only as guidelines.
Other suitable clock layouts may exist and it would be recom-
mended that the board designers simulate to guarantee com-
patibility across all printed circuit and clock component pro-
cess variations.
TERMINATION FOR LVPECL OUTPUTS
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kW resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB401BGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB401BFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB401CGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB401CFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB403DGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB306BLI | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 28TSSOP - Rail/Tube |
| 9DB306BLILF | 功能描述:IC JITTER ATTENUATOR 28-TSSOP 制造商:idt, integrated device technology inc 系列:- 包裝:管件 零件狀態(tài):過期 PLL:是 主要用途:PCI Express（PCIe） 輸入:HCSL，LVDS，LVHSTL，LVPECL，SSTL 輸出:LVPECL 電路數(shù):1 比率 - 輸入:輸出:1：6 差分 - 輸入:輸出:是/是 頻率 - 最大值:140MHz 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:28-TSSOP 標準包裝:50 |
| 9DB306BLILFT | 功能描述:IC JITTER ATTENUATOR 28-TSSOP 制造商:idt, integrated device technology inc 系列:- 包裝:帶卷（TR） 零件狀態(tài):過期 PLL:是 主要用途:PCI Express（PCIe） 輸入:HCSL，LVDS，LVHSTL，LVPECL，SSTL 輸出:LVPECL 電路數(shù):1 比率 - 輸入:輸出:1：6 差分 - 輸入:輸出:是/是 頻率 - 最大值:140MHz 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:28-TSSOP 標準包裝:1,000 |
| 9DB306BLIT | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 28TSSOP - Rail/Tube |
| 9DB306BLLF | 功能描述:時鐘合成器/抖動清除器 2 LVPECL Output PCI- Express Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。