- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25564 > 9DB306BL (INTEGRATED DEVICE TECHNOLOGY INC) 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 PDF資料下載
參數(shù)資料
| 型號： | 9DB306BL |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 4.40 X 9.70 MM, 0.925 MM HEIGHT, TSSOP-28 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 268K |
| 代理商： | 9DB306BL |
ICS9DB306BL REVISION C AUGUST 13, 2009
8
2009 Integrated Device Technology, Inc.
ICS9DB306 Data Sheet
PCI EXPRESS JITTER ATTENUATOR
FIGURE3C.
HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING and VOH must meet the VPP
and V
CMR
input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB401BGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB401BFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB401CGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB401CFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 9DB403DGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB306BLI | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 28TSSOP - Rail/Tube |
| 9DB306BLILF | 功能描述:IC JITTER ATTENUATOR 28-TSSOP 制造商:idt, integrated device technology inc 系列:- 包裝:管件 零件狀態(tài):過期 PLL:是 主要用途:PCI Express（PCIe） 輸入:HCSL，LVDS，LVHSTL，LVPECL，SSTL 輸出:LVPECL 電路數(shù):1 比率 - 輸入:輸出:1：6 差分 - 輸入:輸出:是/是 頻率 - 最大值:140MHz 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:28-TSSOP 標(biāo)準包裝:50 |
| 9DB306BLILFT | 功能描述:IC JITTER ATTENUATOR 28-TSSOP 制造商:idt, integrated device technology inc 系列:- 包裝:帶卷（TR） 零件狀態(tài):過期 PLL:是 主要用途:PCI Express（PCIe） 輸入:HCSL，LVDS，LVHSTL，LVPECL，SSTL 輸出:LVPECL 電路數(shù):1 比率 - 輸入:輸出:1：6 差分 - 輸入:輸出:是/是 頻率 - 最大值:140MHz 電壓 - 電源:2.97 V ~ 3.63 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:28-TSSOP 標(biāo)準包裝:1,000 |
| 9DB306BLIT | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 28TSSOP - Rail/Tube |
| 9DB306BLLF | 功能描述:時鐘合成器/抖動清除器 2 LVPECL Output PCI- Express Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。