參數(shù)資料
型號(hào): 992215732011
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, CDIP32
封裝: CERAMIC, DIP-32
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 234K
代理商: 992215732011
2000 January
7
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FT 18
Figure 4 - Frame timing diagrams
Frame Timing
Frame Shift Timing
A1
L
H
Tp=1/(36MHz) = 27.8ns
A2
L
H
A3
L
H
A4
L
H
1
2
1048
1047
B1
L
H
B2
L
H
B3
L
H
B4
L
H
1
2
1048
1047
48 Tp
750kHz
18Tp
30Tp
for all A and B clocks,
duty cycle = 5/8
1109 1110 1111 1112 1113 1114 1115 1116
1119 1120 1121 1122
...... 1250
1
......
26
27
......
70
71
72
73
74
75
76
77
78
79
80
81
82
83
86
87
1024 D
D
B
BLC BLC
B
D
E
internal
LINE
counter
EEEEBB
BLC BLC
BBD
D
C
1
video
line no.
A1
A2
A3
A4
L
H
L
H
L
H
L
H
B1
B2
B3
B4
L
H
L
H
L
H
L
H
CR
BLC
SSC
PB
L
H
L
H
L
H
L
H
By adding one CR-pulse during the horizontal blanking,
the effective integration time is decreased: "electronic shuttering"
CB
L
H
CR before nominal integration
......
88
2
charge image (all lines) is moved from image to storage
by the image and storage clocks together (see Figure "Frame Shift Timing").
Frame Transfer (FT):
Charge Pump (CP): a measure to reduce dark current due to interface states.
For details see figure 3 "Line and pixel timing diagrams".
Hustle: moving the charge packets of one line from storage to the output register.
For details see figure 3 "Line and pixel timing diagrams".
Linetime: the C-clocks shift charge packets one-by-one to the selected output buffer.
For details see figure 3 "Line and pixel timing diagrams".
Black-Level Clamp (BLC): the video processing clamps the black lines to determine its output zero-level.
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