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參數(shù)資料
| 型號： | 98ULPA877AKILF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 159K |
| 代理商： | 98ULPA877AKILF-T |
12
ICS98ULPA877A
1177F—12/10/09
VDDQ
GND
VIA
CARD
VIA
CARD
BEAD
0603
4.7uF
1206
0.1uF
0603
2200pF
0603
AVDD
AGND
PLL
1
Figure 11. AVDD Filtering
*Place the 2200pF capacitors close to the PLL.
*Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect
trace to one GND via (farthest from PLL).
*Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8
DC max., 600
at 100MHz).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 98ULPA877AH-T | 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 99.272.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.270.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.265.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
| 99.264.3521.9 | 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 98ULPA877AKLF | 功能描述:時鐘驅(qū)動器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877AKLFT | 功能描述:時鐘驅(qū)動器及分配 Low Power 1.8V DDR-I I PLL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| 98ULPA877FHLF | 制造商:Integrated Device Technology Inc 功能描述:MICRON P/N 521-500297 - Tape and Reel |
| 98ULPA877FHLFT | 制造商:Integrated Device Technology Inc 功能描述:MICRON P/N 521-500297 - Tape and Reel |
| 98WF | 制造商:Redington Counters Inc 功能描述:MECHANICAL COUNTER MEASURING W |
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