參數(shù)資料
型號: 98ULPA877AKILF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40
封裝: ROHS COMPLIANT, PLASTIC, MLF-40
文件頁數(shù): 13/14頁
文件大?。?/td> 159K
代理商: 98ULPA877AKILF-T
8
ICS98ULPA877A
1177F—12/10/09
VDD
GND
ICS98ULPA877A
V(CLK)
VDD/2
ICS98ULPA877A
R= 10
Z= 60
C = 10pF
Z= 50
R= 1M
R= 10
L = 2.97"
VTT
Note: VTT =GND
C= 1pF
R= 1M
C= 1pF
SCOPE
GND
Z= 120
GND
Yx, FB_OUTC
Yx, FB_OUTT
tC(N)
tC(N + 1)
tJIT(CC) =tC(N) +tC(N + 1)
Figure 1: IBIS Model Output Load
Figure 2: Output Load Test Circuit
Figure 3: Cycle-to-Cycle Jitter
Parameter Measurement Information
相關(guān)PDF資料
PDF描述
98ULPA877AH-T 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
99.272.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
99.270.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
99.265.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
99.264.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
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