參數(shù)資料
型號: 98ULPA877AKILF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40
封裝: ROHS COMPLIANT, PLASTIC, MLF-40
文件頁數(shù): 2/14頁
文件大?。?/td> 159K
代理商: 98ULPA877AKILF-T
10
ICS98ULPA877A
1177F—12/10/09
Figure 7: Half-Period Jitter
Yx, FB_OUTC
Yx, FB_OUTT
tJIT(HPER_n)
1
fo
tJIT(HPER_n+1)
tJIT(HPER) =tJIT(HPER_n) -
1
2xfo
Clock Inputs
and outputs
20%
80%
tSLR
20%
80%
tSLF
VID VOD
Figure 8: Input and Output Slew Rates
Parameter Measurement Information
相關(guān)PDF資料
PDF描述
98ULPA877AH-T 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
99.272.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
99.270.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
99.265.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
99.264.3521.9 20 A, STRIP TERMINAL BLOCK, 2 ROWS, 1 DECK
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