參數(shù)資料
型號: 9880
廠商: Intel Corp.
英文描述: Advanced 10/100 Repeater with Intergrated Management
中文描述: 高級10/100中繼器與綜合管理
文件頁數(shù): 87/118頁
文件大?。?/td> 1648K
代理商: 9880
Advanced 10/100 Repeater with Integrated Management
LXT9860/9880
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
87
6.0
Register Definitions
6.1
Register Map
The LXT98x0 register set is composed of multiple 32-bit registers as mapped in
Table 45
. All
register addresses are hexadecimal.
Figure 41. PROM Interface Timing
Table 44. PROM Interface Timing Characteristics
Parameter
Sym
Min
Typ
1
Max
Units
Test Conditions
PROM_CLK
1.0
MHz
PROM_CLK frequency.
CLK to PROM_CS delay
t16A
200
ns
CLK falling edge to
PROM_CS.
CLK to PROM_DTOUT delay
t16B
20
ns
CLK falling edge to
PROM_DTOUT.
PROM_DTIN to CLK setup time
t16C
20
ns
PROM_DTIN to CLK rising
edge.
PROM_DTIN to CLK hold time
t16D
20
ns
PROM_DTIN to CLK rising
edge.
1. Typical values are at 25
°
C and are for design aid only; they are not guaranteed and not subject to
production testing.
PROM_DTOUT
PROM_CS
PROM_CLK
t
16A
t
16B
PROM_DTIN
t
16C
t
16D
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