參數(shù)資料
型號(hào)： 9860
廠商： Intel Corp.
英文描述： Advanced 10/100 Repeater with Intergrated Management
中文描述： 高級(jí)10/100中繼器與綜合管理
文件頁數(shù)： 109/118頁
文件大小： 1648K
代理商： 9860
Advanced 10/100 Repeater with Integrated Management
—
LXT9860/9880
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
109
Global LED Control Register
R/W
140
This register reflects the LED Mode set by hardware
pins, and provides software control for the Global Fault
LED. Refer to
Table 78.
Port LED Control Register
R/W
141
This register provides a measure of software control
over the port LEDs. Refer to
Table 81
for bit
assignments. During reset, the state of this register is
all 1s. If a manager is present, this register remains in
the all 1s state after reset. Otherwise, the bits default to
hardware control.
LED Timer Control Register
R/W
142
Refer to
“
LED Timer Control Register
”
on page 112
for
details. Bits 15:8 of this register set the slow blink
frequency of the LEDs. Bits 7:0 set the fast blink
frequency.
Repeater Reset Register
W
144
Writing any data value to this register with the Least
Significant Bit (LSB) = 1 causes the repeater logic to
reset. (All bits other than LSB do not matter.) The
counters and configuration information are held static
and is not reset.
Refer to
Table 83 on page 113
for details.
Software Reset Register
W
145
Writing any data value to this register with the Least
Significant Bit (LSB) = 1 is identical to a hardware
reset. (All bits other than LSB do not matter.) Refer to
Table 84 on page 113
for details.
Assign Address Register
(1 and 2)
W
188, 189
Writing a valid 48-bit ID (one that matches the PROM
ID) to this register causes the device to change its Hub
ID to the contents of the PROM ID register listed below.
This register cannot be read. Refer to
Table 89
and
Table 90,
“
Assign Addr 2
”
on page 116
for details.
PROM Address Register
(1 and 2)
R
190, 191
These two registers contain the 48-bit ID read in from
PROM at power-up. Refer to
Table 91
and
Table 92,
“
PROM Addr 2
”
on page 116
for details.
Table 75. Repeater Configuration Register
Bit
Name
Description
Type
1
Default
31:15
Reserved
Reserved - Write as 0
’
s, ignore on Read
R/W
0
14
Configuration
Mode Select
Configuration Mode Select
0 = 2 bit direct input mode (using CONFIG[1:0])
1 = 8 bit serial bus mode (using CFG_CLK, CFG_DT, CFG_LD)
R/W
0
13
Extended Frame
Extended Frame counting mode
1 = all relevant counters allow max size frames up to 1522
bytes, etherstats counter change from 1518 to 1522
0 = normal mode
R/W
0
1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
2. While the zeroing operation is in progress, the CPU is locked out from accessing the statistics RAM until
the
“
zero counter
”
bit has been reset back to
‘
0
’
. This time period is roughly 15
μ
s.
Table 74. Configuration Registers (Continued)
Name
Type
1
Addr
Description
1. R = Read only; W = Write only; R/W = Read /Write.
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