- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25548 > 97SD3248RPMH (MAXWELL TECHNOLOGIES) 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 PDF資料下載
參數(shù)資料
| 型號(hào)： | 97SD3248RPMH |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | DRAM |
| 英文描述： | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 封裝： | STACK, QFP-132 |
| 文件頁(yè)數(shù)： | 15/40頁(yè) |
| 文件大?。?/td> | 758K |
| 代理商： | 97SD3248RPMH |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)
97SD3248
M
em
o
ry
22
All data sheets are subject to change without notice
2004 Maxwell Technologies
All rights reserved.
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
03.25.04 Rev 1
Write Operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10,
A9, A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set
to 1, 2, 4, or 8, like burst read operations. The write start address is specified by the column address and the
bank select address (BA0/BA1) at the write command set cycle.
2. Single write: A single write operation is enabled by setting OPCODE ( A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA0/BA1) specified by
the write command set cycle without regard to the burst length setting. ( The latency of data input is 0 clock.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 97SD3248RPMI | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 97SD3248RPMK | 32M X 48 SYNCHRONOUS DRAM, 6 ns, QFP132 |
| 97U870AKIT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 97U870AH | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97U870AHIT | 97U SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97SD3248RPQE | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQH | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQI | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SD3248RPQK | 制造商:MAXWELL 制造商全稱:Maxwell Technologies 功能描述:1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks |
| 97SG-1 | 制造商:EECO Switch 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。