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參數(shù)資料
| 型號(hào)： | 951412AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大?。?/td> | 246K |
| 代理商： | 951412AGLF |
9
ICS951412
0883L—04/26/06
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRCCLK7
RW
Disable
Enable
1
Bit 6
SRCCLK6
RW
Disable
Enable
1
Bit 5
SRCCLK5
RW
Disable
Enable
1
Bit 4
SRCCLK4
RW
Disable
Enable
1
Bit 3
SRCCLK3
RW
Disable
Enable
1
Bit 2
SRCCLK0
RW
Disable
Enable
1
Bit 1
REQASRC3
CLKREQA# Controls SRC3
RW
Does not control
Controls
0
Bit 0
REQASRC0
CLKREQA# Controls SRC0
RW
Does not control
Controls
0
SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
REQASRC7
CLKREQA# Controls SRC7
RW
Does not control
Controls
0
Bit 6
REQASRC6
CLKREQA# Controls SRC6
RW
Does not control
Controls
0
Bit 5
REQASRC5
CLKREQA# Controls SRC5
RW
Does not control
Controls
0
Bit 4
REQASRC4
CLKREQA# Controls SRC4
RW
Does not control
Controls
0
Bit 3
ATIGCLK1
RW
Disabled
Enabled
1
Bit 2
ATIGCLK0
RW
Disabled
Enabled
1
Bit 1
Reserved
RW
Reserved
0
Bit 0
USB_48Str
48MHz Strength Control
RW
1X
2X
0
Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.
Behavior of the device is undefined under these conditions.
SMBus Table: Output Drive and ATIG Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
REF2Str
REF2 Strength Control
RW
1X
2X
0
Bit 6
Reserved
RW
Reserved
0
Bit 5
Reserved
RW
Reserved
0
Bit 4
SRC SSEN
SRC Spread Enable
RW
0
Bit 3
SRCFS3
Freq Select Bit 3
RW
0
Bit 2
SRCFS2
Freq Select Bit 2
RW
0
Bit 1
SRCFS1
Freq Select Bit 1
RW
0
Bit 0
SRCFS0
Freq Select Bit 0
RW
0
-
See Table 2:
SRC Frequency Selection
Byte 5
52
-
Output Enable
These outputs cannot be
controlled by CLKREQ# pins.
30,29
-
4
16,17
18,19
22,23
27,28
24,25
34,33
Byte 4
12,13
Byte 3
12,13
Master Output control.
Enables or disables output,
regardless of CLKREQ#
inputs.
16,17
18,19
22,23
24,25
34,33
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