參數(shù)資料
型號(hào): 951412AGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件頁(yè)數(shù): 20/25頁(yè)
文件大?。?/td> 246K
代理商: 951412AGLF
4
ICS951412
0883L—04/26/06
General Description
The ICS951412 is a main clock synthesizer chip that provides all clocks required for ATI RS480-based systems.
An SMBus interface allows full control of the device.
Skew Characteristics
Parameter
Description
Test Conditons
Skew
Window
Unit
Tsk_CPU_CPU
measured at x-ing of CPU,
250
ps
Tsk_CPU_PCI
measured at x-ing of CPU,
1.5V of PCI clock
2000
ps
Tsk_PCI_PCI
measured between rising
edge at 1.5V
500
ps
Tsk_PCI33-HT66
measured between rising
edge at 1.5V
500
ps
Tsk_CPU_HT66
measured between rising
edge at 1.5V
2000
ps
Tsk_CPU_HT66
measured at x-ing of CPU,
1.5V of PCI clock
500
ps
Tsk_CPU_CPU
measured at x-ing of CPU,
200
ps
Tsk_CPU_PCI
measured at x-ing of CPU,
1.5V of PCI clock
200
ps
Tsk_PCI_PCI
measured between rising
edge at 1.5V
200
ps
Tsk_PCI33-HT66
measured between rising
edge at 1.5V
200
ps
Tsk_CPU_HT66
measured between rising
edge at 1.5V
200
ps
Tsk_CPU_HT66
measured at x-ing of CPU,
1.5V of PCI clock
200
ps
time independent
skew
not dependent on
V, T changes
time variant skew
varies over
V, T changes
Block Diagram
MAIN PLL
PCICLK0
CONTROL
LOGIC
XTAL
OSC.
CPUCLK8(1:0)
FIXED PLL
USB_48MHz
DIVIDER
DIVIDERS
REF(2:0)
HTTCLK0
SRCCLK(7:3,0)
CLKREQA#
SDATA
SCLK
FS(2:0)
CLKREQB#
SEL75#/100
X1
X2
IREF
ATIGCLK(1:0)
相關(guān)PDF資料
PDF描述
951413CGLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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951413CFLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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