參數(shù)資料
型號: 93LC56C
廠商: Microchip Technology Inc.
元件分類: EEPROM
英文描述: 2K Microwire Compatible Serial EEPROM
中文描述: 2K微絲兼容串行EEPROM
文件頁數(shù): 7/28頁
文件大小: 357K
代理商: 93LC56C
2007 Microchip Technology Inc.
DS21794E-page 7
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4
Erase
The
ERASE
instruction forces all data bits of the speci-
fied address to the logical ‘
1
’ state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘
0
’ indicates that programming
is still in progress. DO at logical ‘
1
’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
FIGURE 2-1:
ERASE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-2:
ERASE TIMING FOR 93C DEVICES
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
1
1
1
A
N
A
N
-1
A
N
-2
A0
T
SV
T
CZ
Busy
Ready
High-Z
T
WC
High-Z
CS
CLK
DI
DO
T
CSL
Check Status
1
1
1
A
N
A
N
-1
A
N
-2
A0
T
SV
T
CZ
Busy
Ready
High-Z
T
WC
High-Z
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