參數(shù)資料
型號: 935273916557
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PBGA156
封裝: 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù): 109/178頁
文件大小: 988K
代理商: 935273916557
2004 Jul 22
36
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
8.1.4
CLOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for
the video input processor.
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:
6.75 MHz = 429
× f
H (50 Hz), or
6.75 MHz = 432
× f
H (60 Hz).
The LFCO signal is multiplied by a factor of 2 and 4 in the
internal PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50% duty
factor.
Table 3
Decoder clock frequencies
CLOCK
FREQUENCY (MHz)
XTALO
24.576 or 32.110
LLC
27
LLC2
13.5
LLC4 (internal)
6.75
LLC8 (virtual)
3.375
Fig.21 Block diagram of the clock generation circuit.
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
DIVIDER
1/2
DIVIDER
1/2
OSCILLATOR
MHB330
LLC2
LLC
LFCO
8.1.5
POWER-ON RESET AND CHIP ENABLE (CE) INPUT
A missing clock, insufficient digital or analog VDDA0 supply
voltages (below 2.8 V) will start the reset sequence; all
outputs are forced to 3-state (see Fig.22). The indicator
output RES is LOW for approximately 128 LLC after the
internal reset and can be applied to reset other circuits of
the digital TV system.
It is possible to force a reset by pulling the Chip Enable pin
(CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA
return from 3-state to active, while the other signals have
to be activated via programming.
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