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參數(shù)資料
| 型號： | 935270050128 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 26/55頁 |
| 文件大小： | 706K |
| 代理商： | 935270050128 |
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Philips Semiconductors
SC16C654/654D
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 02 — 13 March 2003
32 of 52
9397 750 10985
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
When using software ow control the Xon/Xoff characters cannot be used for data transfer.
5
EFR[5]
Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C654/654D
compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to FIFO and ISR[4] will be
set to indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this
feature is enabled, the normal software ow control must be disabled
(EFR[3-0] must be set to a logic 0).
4
EFR[4]
Enhanced function control bit. The content of IER[7-4], ISR[5-4],
FCR[5-4], and MCR[7-5] can be modied and latched. After modifying
any bits in the enhanced registers, EFR[4] can be set to a logic 0 to latch
the new values. This feature prevents existing software from altering or
overwriting the SC16C654/654D enhanced functions.
Logic 0 = Disable (normal default condition).
Logic 1 = Enable.
3-0
EFR[3-0]
Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software ow control can be selected by programming
these bits. See Table 23.
Table 23:
Software ow control functions[1]
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software ow controls
0
X
No transmit ow control
1
0
X
Transmit Xon1/Xoff1
0
1
X
Transmit Xon2/Xoff2
1
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
0
No receive ow control
X
1
0
Receiver compares Xon1/Xoff1
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Table 22:
Enhanced Feature Register bits description…continued
Bit
Symbol
Description
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