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參數(shù)資料
| 型號(hào)： | 935269148518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-96, SO-8 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 178K |
| 代理商： | 935269148518 |
Philips Semiconductors
Product data
NE56605-42
System reset with built-in watchdog timer
2001 Aug 22
5
AC ELECTRICAL CHARACTERISTICS
Characteristics measured with VCC = 5.0 V, and Tamb = 25 °C, unless otherwise specified.
See Figure 24 (Test circuit 2) for test configuration used for AC parameters.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
tP1
Minimum power supply pulse width for
detection
4.0 V
≤ negative-going VCC pulse ≤ 5.0 V
8.0
–
s
tCLKW
Clock input pulse width
3.0
–
s
tCLK
Clock input cycle
20
–
s
tWDM
Watchdog monitoring time (Notes 1, 6)
CT = 0.1 F; RCT = open
5.0
10
15
ms
tWDR
Watchdog reset time (Notes 2, 6)
CT = 0.1 F
1.0
2.0
3.0
ms
tPR
Power-on reset delay time (Notes 3, 6)
VCC = rising from 0 V; CT = 0.1 F
50
100
150
ms
tPD1
RESET, RESET propagation delay time
(Note 4)
RESET: RL1 = 2.2 k; CL1 = 100 pF
–
2.0
10
s
tPD2
(Note 4)
RESET: RL2 = 10 k; CL2 = 20 pF
–
3.0
10
s
tR1
RESET, RESET rise time (Note 5)
RESET: RL1 = 2.2 k; CL1 = 100 pF
–
1.0
1.5
s
tR2
RESET: RL2 = 10 k; CL2 = 20 pF
–
1.0
1.5
s
tF1
RESET, RESET fall time (Note 5)
RESET: RL1 = 2.2 k; CL1 = 100 pF
–
0.1
0.5
s
tF2
RESET: RL2 = 10 k; CL2 = 20 pF
–
0.5
1.0
s
NOTES:
1. ‘Watchdog monitoring time’ is the duration from the last pulse (negative-going edge) of the timer clear clock pulse until reset output pulse
occurs (see Figure 18). A reset signal is output if a clock pulse is not input during this time.
2. ‘Watchdog reset time’ is the reset pulse width (see Figure 18).
3. ‘Power-on reset delay time’ is the duration measured from the time VCC exceeds the upper detection threshold (VSH) and power-on reset
release is experienced (RESET output HIGH; RESET output LOW).
4. ‘RESET, RESET propagation delay time’ is the duration from when the supply voltage sags below the lower detection threshold (VSL) and
reset occurs (RESET output LOW, RESET output HIGH).
5. RESET, RESET rise and fall times are measured at 10% and 90% output levels.
6. Watchdog monitoring time (tWDM), watchdog reset time (tWDR), and power-on reset delay time (tPR) during power-on can be modified by
varying the CT capacitance. The times can be approximated by applying the following formula. The recommended range for CT is 0.001 F
to 10
F.
Formula 1.
Calculation for approximate tPR, tWDM, and tWDR values:
tPR (ms) ≈ 1000 × CT (F)
tWDM (ms) ≈ 100 × CT (F)
tWDR (ms) ≈ 20 × CT (F)
Example:
When CT = 0.1 F and WDC = open:
tPR ≈ 100 ms
tWDM ≈ 10 ms
tWDR ≈ 2.0 ms
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