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參數(shù)資料
| 型號： | 935267864118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大小： | 138K |
| 代理商： | 935267864118 |
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Philips Semiconductors
Product data
PCA9504A
Glue chip 4
2002 Mar 28
4
PIN DESCRIPTION CONTINUED
PIN(S)
SYMBOL
FUNCTION
50
3I
VSYNC_3V
VSYNCH input from chipset video
51
5O
HSYNC_5V
HSYNCH output to monitor
52
5O
VSYNC_5V
VSYNCH output to monitor
53
AI
VCCP_VREF
Analog voltage reference for determining INIT/A20M input thresh-
olds
54
3IV/3O
STRAP
Strapping option for GP or FLUSH mode
55
5I
GP3_IN
Generic logic gate 3 input
56
5V OD
GP3_OUT
Generic logic gate 3 output
TYPE
DESCRIPTION
3I
3.3 V input signal
3IU
3.3 V input signal with internal pull-up
5I
5 V input signal
5IU
5 V input signal with internal pull-up
5ID
5 V input signal with internal pull-down
P
Power (input)
G
Ground (input)
3O
3.3 V output signal
5O
5 V output signal
3V OD
3.3 V open-drain output signal
5V OD
5 v open-drain output signal
AO
Analog output
AI
Analog input
3IOD
3.3 V input/output open-drain
5IOD
5 V input/output open-drain
REFL
Input voltage levels referenced to VCCP_VREF
FUNCTION TABLES
Strapping Selection Pin
STRAP (pin 54)
MODE1
PIN NAME & (PIN NUMBER)
0
FLUSH
GPO_FLUSH_CACHE (4)
0
FLUSH
A20M (5)
0
FLUSH
INIT (6)
0
FLUSH
FLUSH_OUT_CPU (7)
0
FLUSH
INIT_OUT (8)
1
GP
GP2_IN (4)
1
GP
GP1_INB (5)
1
GP
GP1_INA (6)
1
GP
GP1_OUT (7)
1
GP
GP2_OUT (8)
NOTE:
1. The pin is internally pulled up to default to FLUSH mode.
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