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參數(shù)資料
| 型號(hào)： | 935267864118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56 |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | 935267864118 |
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Philips Semiconductors
Product data
PCA9504A
Glue chip 4
2002 Mar 28
3
PIN DESCRIPTION
PIN(S)
SYMBOL
FUNCTION
1
3I
VREF3IN
3.3 V input
2
P
V_5P0_STBY
5 V system standby power supply
3
P
V_3P3_STBY
3 V system standby power supply
4
3IU
GPO_FLUSH_CACHE / GP2_IN
GPO from SIO / ICH2 / Buffer 2 input
5
REF
A20M / GP1_INB
A20M signal from ICH2 / NAND 1 input B
6
REF
INIT / GP1_INA
INIT signal from the ICH2 / Buffer 1 input A
7
5V OD
FLUSH_OUT_CPU / GP1_OUT
Open drain signal, goes to the CPU / NAND 1 output
8
5V OD
INIT_OUT / GP2_OUT
Delayed INIT signal into the CPU / Buffer 2 output
9
3I
CLK_IN
Either 33MHz or 66MHz clock, based on SEL_33_66 pin
10
3IU
SEL_33_66
Strapping option for 33MHz or 66MHz CLK_IN
11, 29, 43
G
GND
Ground
12
3I
PCRIST
PCI reset signal
13
3O
PCRIST_OUT
Copy of PCRIST, increased drive-strength
14
3IU
AUD_EN
Audio enable input (GPO from ICH2 / SIO)
15
3O
AUD_RST
Audio reset output
16
5O
IDE_RSTDRV
IDE reset output, 5 V push/pull
17
3IOD
3V_DDCSCL
DDCSCL input/output 3.3 V side
18
5IOD
5V_DDCSCL
DDCSCL input/output 5 V side
19
3IOD
3V_DDCSDA
DDCSDA input/output 3.3 V side
20
5IOD
5V_DDCSDA
DDCSDA input/output 5 V side
21
3IU
CPU_PRESENT
CPU present signal from the processor
22
3I
SLP_S3
Signal from ICH2 for transitioning to the S3 power state
23
5V OD
PS_ON
Power supply turn-on signal
24
5V OD
HD_LED
Hard drive front panel LED output
25
5IU
PRIMARY_HD
IDE primary drive active input
26
5IU
SCSI
SCSI drive active input
27
5IU
SECONDARY_HD
IDE secondary drive active input
28
5V OD
BACKFEED_CUT
Signal used for STR circuitry
30
5O
LATCHED_BACKFEED_CUT
Signal used for STR circuitry
31
5V OD
FLUSH_OUT_FWH
Open drain signal, goes to the FWH
32
5IU
PWRGD_PS
Power good signal from power supply
33
5IU
FPRST
Reset signal from the front panel
34
3O
PWRGD_3V
3.3 V power good output
35
5V OD
SCK_BJT_GATE
Gate signal from the SCK BJT in suspend to RAM
36
3I
SLP_S5
Signal from the ICH2 for transitioning to the S5 power state
37
3IU
GRN_BLNK
Power LED input, from SIO GPIO
38
3IU
YLW_BLNK
Power LED input, from SIO GPIO
39
5V OD
YLW_LED
Power LED output
40
5V OD
GRN_LED
Power LED output
41
5ID
TEST_EN
Test enable, 100K internal pull-down to GND
42
3O
RSMRST
Reset for the ICH2 resume well
44
AO
REF5V
Highest system supply reference voltage
45
5I
VREF5IN
5V system primary supply input
46
3IU
MUTE_AUD
Signal from SIO to mute audio on power up/down
47
5O
AUD_SHDN
Signal to audio amp to signal shutdown
48
AO
REF5V_STBY
Highest system standby voltage
49
3I
HSYNC_3V
HSYNCH input from chipset video
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